cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 54

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2-16
RAI (Yellow Alarm)
The Yellow alarm is contained in the X1 and X2 bits (by setting them to 0). The
Yellow alarm is controlled by TxAlm[1:0] regardless of X bits source settings. Setting
the TxAlm bit pair to 01 sends the Yellow alarm. X1 and X2 bits are sent as 0 as long
as the TxAlm bit pair is set to 01. The start and termination of RAI occur in the next
frame after setting the TxAlm[1:0] bits.
AIS
The DS3 AIS signal has a valid M-frame alignment channel, a valid M-subframe
alignment channel and valid P-bits, all C-bits set to 0 regardless of DS3 framing mode
(M13/M23 or C-bit parity), both X-bits set to 1, and the payload set to a 1010...
pattern starting with 10 after each Overhead bit.
Generation and transmission of the AIS signal is enabled by setting the TxAlm[1:0]
bit pair to 11. It continues as long TxAlm[1:0] bits are set to 11. When TxAlm[1:0] bit
pair is set to 11, the transmit line output is replaced with the DS3 AIS pattern. The
pattern is generated internally regardless of the inserted data and Overhead bits
insertion method from the system side, which is ignored by the framer.
IDLE
The DS3 IDLE signal has valid framing and parity. With both X-bits set to 1, the
payload is set to a 1100... pattern, starting with 11 after each Overhead bit. The C-bits
in M-subframe 3 are set to 0, and the remaining C-bits can individually be a 1 or a 0,
and can vary with time.
The transmission of idle code is enabled by setting the TxAlm[1:0] bit pair to 10 for
each framer individually, and continues as long as those bits are set to 10. The start
and termination of IDLE generation are frame-aligned (IDLE transmission initiates
with the beginning of the next frame after setting the TxAlm[1:0] bit pair to 10, and
terminates at the beginning of the next frame after setting the TxAlm[1:0] bit pair to
other than 10).
In both DS3 framing modes (M13/M23 or C-bit parity), when IDLE code generation
is enabled, the framer’s transmitter line output is replaced with the DS3 IDLE pattern.
It is internally generated regardless of the inserted data. The C bits are handled as
follows: the C bits in M-subframe 3 are set to 0 and the remaining C bits are set
according to their method of generation setting (from Internal-Auto, from Internal-
Reg, from External-data, or from External-Pin) that are set for each mode, described
in
code specifications. When the transmitter starts generating the IDLE alarm, the
transmitter keeps the previous M-frame’s synchronization.
Handling of the C-bits in IDLE code generation is such to allow full use of the
remaining C-bits, e.g., use terminal data link and transmit FEAC channel in C-bit
parity mode during transmission of IDLE code.
NOTE:
Section 2.1.1.3.
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
When the transmitter starts generating the AIS alarm, it continues keeping the old M-
frame’s synchronization. The start and termination of AIS generation are frame-
aligned (AIS transmission initiates with the beginning of the next frame after setting
the TxAlm[1:0] bit pair to 11, and terminates at the beginning of the next frame after
setting TxAlm[1:0] bit pair to other than 11).
The remaining Overhead bits are generated according to IDLE
CX28365/6/4 Data Sheet
500028C