cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 94

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.3.2
2-56
UTOPIA 8-bit and 16-bit Bus Widths
The CX2836x has two bus width options, 8-bit or 16-bit, which are selected in
BusWidth, bit 2, of the MODE register (0x0202). The protocols and timing are the
same in both modes, except that 8-bit mode uses only the lower half of the data bus
(UTxData[7:0] and URxData[7:0]) and parity is only generated or checked over
those bits.
In 8-bit mode, each ATM cell consists of 53 bytes, as listed
five bytes are used for header information. The remaining bytes are used for payload.
Table 2-12. Cell Format for 8-bit Mode
In 16-bit mode, the cells consists of 54 bytes, as listed in
bytes contain header information. The sixth byte, UDF2, is required to maintain
alignment but is not read by the CX2836x. The remaining bytes are used for payload.
Table 2-13. Cell Format for 16-bit Mode
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
Bit 7
Bit 15
UDF1 (HEC) (byte 5)
Mindspeed Technologies™
Normally, the HEC is calculated by the PHY and put in byte 5, UDF1. However, setting
bit 7 of the CGEN register (0x08) to 1 disables HEC calculation. In this case, data
inserted by the ATM layer into byte 5 is transmitted by the PHY.
UDF1 (HEC) (byte 5)
Payload 48
Payload 1
Header 1
Header 2
Header 3
Header 4
Payload 47
Payload 1
Header 1
Header 3
...
...
...
...
Bit 0
Bit 8
Bit7
Table
UDF2 (0) (byte 6)
inTable
Payload 48
Payload 2
Header 2
Header 4
2-13. The first five
...
...
CX28365/6/4 Data Sheet
2-12. The first
Bit 0
500028C