cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 135

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
3.2.4
0x0D—UTOP1 (UTOPIA Control Register 1)
TxReset
RxReset
OddEven
TxFill[1:0]
0x0E—UTOP2 (UTOPIA Control Register 2)
UtopDis
MphyAddr[4:0]
500028C
TxReset
—
7
7
(1)
(1)
(1)
(1)
When written to a logical 1, this bit resets the transmit FIFO pointers. This reset should only be
used as a test function because it can create short cells.
When written to a logical 1, this bit resets the receive FIFO pointers. This reset should only be
used as a test function because it can create short cells.
This bit determines Odd/Even Parity. When written to a logical 1, even parity is generated and
checked. When set to a logical 0, odd parity is generated and checked.
These bits set the Transmit FIFO Fill-level threshold for UTxCLAV pin
00 = UTxCLAV indicates full after 1 more cell
01 = UTxCLAV indicates full after 2 more cells
10 = UTxCLAV indicates full after 3 more cells
11 = UTxCLAV indicates full after 4 more cells
When written to a logical 1, this bit disables UTOPIA outputs for this port.
These bits are the Multi-PHY Device Address. Each CX2836x port should have a unique
address. These bits correspond to the URxAddr and UTxAddr pins. When the pin matches the
bit values, the port is accessed. This port ignores any transactions meant for another port or
PHY device.
RxReset
NOTE:
NOTE:
UTOPIA Registers
—
6
6
The UTOP1 register controls the UTOPIA resets, parity orientation, and the transmit
FIFO fill-level threshold.
Default after reset: 00
The UTOP2 register contains the multi-PHY address value for the device.
Default after reset: UtopDis set to 1, MphyAddr[4:0] see notes
Preliminary Information/Mindspeed Proprietary and Confidential
(1)
(1)
asserted.
The default for MphyAddr4 is 0 and the default for MphyAddr[3:0] is the port number
for each port. (0000–Port 0, 0001–Port 1, 0010–Port2, 0011–Port 3, 0100–Port 4,
0101–Port 5, 0110–Port 6, 0111–Port 7, 1000–Port 8, 1001–Port 9, 1010–Port10,
1011–Port 11).
UtopDis
These bits should only be changed when the device or port logic reset is asserted.
These bits should only be changed when the Device or Port Logic reset is
—
5
5
Mindspeed Technologies™
MphyAddr[4]
—
4
4
MphyAddr[3]
—
3
3
MphyAddr[2]
OddEven
2
2
MphyAddr[1]
TxFill[1]
1
1
MphyAddr[0]
TxFill[0]
0
0
Registers
3
-
25