cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 182

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x51—SR17 (Receive FEAC Status Register)
RxFEACSNE
RxFEACIdle
RxFEACltr
0x52—SR18 (Receive AIC Byte)
RxAIC[7:0]
3-72
RxAIC[7]
—
7
7
RxAIC[6]
Receive FEAC Stack Is Not Empty—Set due to detection of the FEAC stack being not empty
(i.e., Receive FEAC Stack byte is holding valid data).
Received FEAC Channel Is Idle—In DS3-C-Bit Parity mode, set when the FEAC receiver
detects the first appearance of an Idle code, after reception of legal code words. This bit is
cleared when this register is read. In DS3-M13/M23 and both E3 modes, this bit should be
ignored.
Receive FEAC Channel Interrupt—In DS3-C-Bit Parity mode, when working in FEAC single
mode, set high when an FEAC message byte has been received and placed in the Receive
FEAC Channel Byte register. When working in FEAC repetitive mode, set high when the
receiver detects an FEAC message byte (see Far-End Alarm and Control Channel Reception
paragraph). Reading the Receive FEAC Channel Byte register clears this interrupt. In DS3-
M13/M23, E3-G.751 and E3-G.832 modes, this bit should be ignored.
Receive AIC Channel Message Byte—If the incoming format is DS3, C-Bit Parity, this
register contains 8 AIC (Cb11) bits from 8 consecutive frames. RxAIC[0] is the first bit
received and RxAIC[7] is the last bit received from the line. This byte is meaningless in DS3-
M13/M23 and both E3 modes and should be ignored.
—
6
6
Value after reset: 00
Direction: Read only
Value after enable: 00
Value after reset: Undefined
Direction: Read only
Value after enable: Unaffected
Preliminary Information/Mindspeed Proprietary and Confidential
RxAIC[5]
—
5
5
Mindspeed Technologies™
RxAIC[4]
—
4
4
RxAIC[3]
—
3
3
RxFEACSNE
RxAIC[2]
2
2
RxFEACIdle
RxAIC[1]
1
1
CX28365/6/4 Data Sheet
RxFEACltr
RxAIC[0]
0
0
500028C