cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 163

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
3.4.3
0x2B—CR11 (REXTCK Control Register)
ExtReserved/GC
ExtDL/NR
ExtFEBE/A
ExtCP/TM
ExtFEAC/PD/Stf
ExtAIC/Cj/TR
500028C
ExtReserved/
GC
7
ExtDL/NR
External Reserved C-bits/GC Byte—Set to enable presentation of reserved C-bits (C12, C2,
C6, C7) in DS3-C-Bit Parity mode or presentation of GC byte in E3-G.832 mode through
REXTCKO pin. In DS3-M13/M23 and E3-G.751 modes, this bit is ignored.
External Data Link/NR Byte—Set to enable presentation of data link data through REXTCKO
pin. The bits are output exactly as they were received (i.e., the HDLC circuit is bypassed). In
DS3-C-Bit Parity mode, this bit enables presentation of C5 bits through REXTCKO pin. In E3-
G.751 mode, this bit enables presentation of N-bit through REXTCKO pin. In E3-G.832 mode,
this bit enables presentation of NR byte through REXTCKO pin. In DS3-M13/M23, this bit is
ignored.
External FEBE/REI/A-Bit—Set to enable presentation of FEBE field in DS3-C-Bit Parity
mode or REI bit field in E3-G.832 mode through the REXTCKO pin. In E3-G.751 mode, set
to enable presentation of A-bit through REXTCKO pin. In DS3-M13/M23 mode, this bit is
ignored.
External Path Parity/Timing Marker/SSM—Set to enable presentation of CP field in DS3-C-
Bit Parity mode or Timing Marker/SSM bit field in E3-G.832 mode through REXTCKO pin.
In DS3-M13/M23 and E3-G.751 modes, this bit is ignored.
External FEAC/Payload Dependent/Multiframe Indicator/Stuff Opportunity Bits—Set to
enable presentation of FEAC channel in DS3-C-Bit Parity mode or payload dependent/
multiframe indicator field in E3-G.832 mode or Stuff Opportunity bits in DS3 M13/M23 and
in E3-G.751 modes through REXTCKO pin.
External AIC/Justification Control/Trail Trace—In DS3-C-Bit Parity mode, set to enable
presentation of application identification channel through REXTCKO pin. In DS3-M13/M23
and E3-G.751 modes, set to enable presentation of the Justification Control bits through the
REXTCKO pin. In E3-G.832 mode, set to enable presentation of Trail Trace byte through
REXTCKO pin.
Receiver Registers
6
The REXTCK Control register provides enabled marking of different fields through
REXTCKO pin. Presentation of a field through REXTCKO pin does not prevent it
from being ticked upon by the RxGCKO pin or from being processed via the
microprocessor interface. Setting a bit in this register does not affect other control bits
set in other registers. This enables monitoring of certain fields for testing, in addition
to being processed by another mechanism. If a specific field should be presented only
through the REXTCKO pin, it should be disabled from being presented on RxGCKO/
microprocessor interface in another control register.
Default after reset: 00
Direction: Read/Write
Modification: Static
Preliminary Information/Mindspeed Proprietary and Confidential
ExtFEBE/A
5
Mindspeed Technologies™
ExtCP/TM
4
ExtFEAC/PD/
Stf
3
ExtAIC/Cj/TR
2
ExtFrm
1
AllRxExt
0
Registers
3
-
53