cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 31

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
Table 1-4. Hardware Signal Definition, ATM UTOPIA Interface (2 of 2)
500028C
URxAddr[0]
URxAddr[1]
URxAddr[2]
URxAddr[3]
URxAddr[4]
URxData[0]
URxData[1]
URxData[2]
URxData[3]
URxData[4]
URxData[5]
URxData[6]
URxData[7]
URxData[8]
URxData[9]
URxData[10]
URxData[11]
URxData[12]
URxData[13]
URxData[14]
URxData[15]
URxPrty
URxSOC
URxCLAV
Label
Pin
UTOPIA Receive
Address
UTOPIA Receive Data
UTOPIA Receive Parity
Input
UTOPIA Receive Start
of Cell
UTOPIA Receive Cell
Available
Signal
Name
Preliminary Information/Mindspeed Proprietary and Confidential
CX28365
Pin#
A18
B18
B17
B16
C16
B23
C21
D20
B22
C20
D19
B21
C19
D18
B20
C18
D17
B19
C17
D16
D15
A23
A24
B24
Mindspeed Technologies™
CX28366
Pin#
A18
B18
B17
B16
C16
B24
B23
C21
D20
B22
C20
D19
B21
C19
D18
B20
C18
D17
B19
C17
D16
D15
A23
A24
CX28364
Pin#
A18
B18
B17
B16
C16
B24
B23
C21
D20
B22
C20
D19
B21
C19
D18
B20
C18
D17
B19
C17
D16
D15
A23
A24
O/Z
O/Z
O/Z
O/Z
I/O
I
Address of the PHY device being selected
for reception. The address range is 0–30.
Address 11111(31 decimal) indicates a
null PHY port. Schmitt trigger input.
These pins output the received data to the
ATM layer.
Parity calculated over the URxData bus.
BusWidth (bit 0) in the SYSBUS register
(0xE01) determines whether parity is
calculated over URxData[7:0] or
URxData[15:0]. OddEven (bit 2) in the
UTOP1 register determines whether this
pin represents even or odd parity.
When active high, this pin indicates the
first byte of valid cell data received. An
external pulldown resistor is required for
this pin.
Indicates FIFO empty or Cell Buffer.
Available, depending upon HandShake
(bit 1) in the SYSBUS register (0xE01).
An external pulldown resistor is required
for this pin.
Definition
Product Description
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