cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 72

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.1.2.4
2-34
The AIC bit (Cb11) in DS3 C-bit parity is always 1; while the same bit in DS3 M13/
M23, being a justification bit, is either 0 or 1. An 8-bit register (ReceiveAICByte
Status register) containing the AIC bits from eight consecutive frames is provided for
polling and system verification of the bit.
Internal processing of the terminal data link bits (i.e., Cb5, N-bit, NR, and GC) as
HDLC/LAPD channels makes their contents available to the system through an
internal 128-byte FIFO buffer; this mechanism is fully described in
is not possible to use this internal mechanism for non-HDLC channels.
Messages flowing on the FEAC (Cb13) channel are supplied to the system via a
dedicated register.
Non-alarm fields of the MA byte (i.e., PT, PD/MI, and TM/SSM) are available for
inspection through the microprocessor interface. Their contents (three bits for PT, two
bits for PD/MI, one bit for TM, and four bits for SSM) are saved on every E3-G.832
frame in dedicated registers (RxMAPT, RxMAPD, and RxMATM fields of the E3-
G.832 MAFields Status register; RxSSM field of the E3-G.832 SSMField Status
register). The host processor poll these fields to detect changes in their values. The
RxSSM field, on a multiframe boundary (i.e., when MI is 11), stores the 4-bit SSM
field, spread over a four-framed multiframe based on the MI field. Selection of
whether the framer functions in TM or SSM mode is through the SSMEn field of the
Feature4 Control register.
There is no internal processing of justification control, Stuff Opportunity, reserved,
and TR fields.
Performance Monitoring
The performance monitoring function is available through event indicators, counters,
and interrupts. An event indicator represents an event, such as parity error, or a
change of status, such as out-of-frame. These event indicators can be the cause for an
interrupt or the increment of a event counter. The event indicators are BPV , EXZ,
LCV, FBE, PER, PBD, PPER, XBD, FEBE/REI, LOS, OOF, SEF, AIS, IDLE, and
RAI/RDI.
These event indicators are externally identifiable through interrupts, counters, or the
status registers they affect. All counters used to count the events are 16 bits long
except the LCV counter, which is 24 bits long. If these counters are read once per
second, the size of the counters guarantees non-saturation in normal conditions
(assuming a BER 1E3).
Depending on the settings of the Counter Interrupt Control register, the counters
function either in saturation mode or rollover mode.
If the interrupt associated with a specific counter is masked, the counter operates in
saturation mode. In this mode, the counter counts up to the highest possible value and
turns on a saturation indication bit in the Counter Interrupt Status register. The
counter and the indication bits are cleared when read.
If the interrupt associated with a specific counter is unmasked, the counter operates in
the rollover mode and resumes counting from zero after counting up to the highest
value. An interrupt is generated, and an interrupt identification bit is set in the Counter
Interrupt Status register. The counter and the status register are cleared when read.
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
CX28365/6/4 Data Sheet
Section
2.1.2.5. It
500028C