cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 153

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
0x23—CR03 (Alarm End Interrupt Control Register)
LOSEndIE
IdleEndIE
YelEndIE
AISEndIE
OOFEndIE
500028C
—
7
Loss of Signal End Interrupt Enable—Set to enable interrupts to be asserted on MINTR* pin
due to detection of LOS condition end in all modes. When a LOS condition end is detected, the
interrupt is asserted, and LOSEnd bit in Alarm End Interrupt Status register is set. When this
bit is cleared, detection of LOS end sets the appropriate status bit; however, an interrupt is not
activated.
Idle Interrupt End Enable—Set to enable interrupts be asserted on MINTR* pin due to
detection of Idle event end in DS3 mode. When the receiver detects an Idle end, the interrupt is
asserted, and IdleEnd bit in Alarm End Interrupt Status register is set. When this bit is cleared,
detection of Idle end sets the appropriate status bit; however, an interrupt is not activated. This
bit has no effect in E3-G.751 and E3-G.832 modes.
Yellow Alarm End Interrupt Enable—Set to enable interrupts to be asserted on MINTR* pin
due to detection of RAI/RDI event end in all modes. When the receiver detects an RAI/RDI
event end, the interrupt is asserted, and YelEnd bit in Alarm End Interrupt Status register is set.
When this bit is cleared, detection of RAI/RDI end sets the appropriate status bit; however, an
interrupt is not activated.
Alarm Indication Signal End Interrupt Enable—Set to enable interrupts to be asserted on
MINTR* pin due to detection of AIS event end in all modes. When the receiver detects an AIS
event end, the interrupt is asserted, and AISEnd bit in Alarm End Interrupt Status register is
set. When this bit is cleared, detection of AIS end sets the appropriate status bit; however, an
interrupt is not activated.
Out of Frame End Interrupt Enable—Set to enable interrupts be asserted on MINTR* pin due
to detection of OOF condition end in all modes. When the receiver detects an OOF condition
end, the interrupt is asserted, and OOFEnd bit in Alarm End Interrupt Status register is set.
When this bit is cleared, detection of OOF end sets the appropriate status bit; however, an
interrupt is not activated.
—
6
Default after reset: 00
Direction: Read/Write
Modification: Dynamic
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
—
5
Mindspeed Technologies™
Reserved bits in Control registers must be set to 0.
LOSEndIE
4
IdleEndIE
3
YelEndIE
2
AISEndIE
1
OOFEndIE
0
Registers
3
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43