cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 169

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
0x32—CR17 (Receive Data Link Threshold Control Register)
RxNFThr [6:0]
0x33—CR18 (Transmit FEAC Channel Byte)
TxFEAC[7:0]
500028C
TxFEAC[7]
—
7
7
RxNFThr[6]
TxFEAC[6]
Receive Data Link FIFO Near Full Threshold—Set to the threshold value; used to indicate a
near-full FIFO event. The range of values available for this purpose is 2–127, where 02(h) is
interpreted as 2 and 7F(h) is interpreted as 127.
Transmit FEAC Channel Message Byte—If the mode is set to DS3-C-Bit Parity, this register is
used as the data byte for the transmit FEAC channel transmitter. When this byte is in the form
0xxxxxx0 it is transmitted after every flag. If there is a 1 in either the most significant or least
significant bit of this register, an all-1s (idle) is transmitted on FEAC channel. An interrupt is
associated with this channel and is enabled by TxFEACIE bit in Feature3 Control register. For
interrupt activation. TxFEAC [0] bit is transmitted first and TxFEAC [7] bit is transmitted last.
6
6
Default after reset: 7F
Direction: Read/Write
Modification: DL—static
Default after reset: FF
Direction: Read/Write
Modification: Dynamic
Preliminary Information/Mindspeed Proprietary and Confidential
RxNFThr[5]
TxFEAC[5]
5
5
Mindspeed Technologies™
RxNFThr[4]
TxFEAC[4]
4
4
RxNFThr[3]
TxFEAC[3]
3
3
RxNFThr[2]
TxFEAC[2]
2
2
RxNFThr[1]
TxFEAC[1]
1
1
RxNFThr[0]
TxFEAC[0]
0
0
Registers
3
-
59