cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 41

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
2.1
2.1.1
2.1.1.1
Figure 2-2. Transmitter Line Outputs
2.1.1.2
500028C
Shown for [CR05 . LTx Ck Ris] = 0
TxNEGO
TxPOSO
TxCKO
T3/E3 Framer
Transmitter Operation
The following describes the transmitter and receiver operation for a single framer. All
features are the same for all the ports in the device.
Line Signals
The transmit line side interface consists of three output pins: TxPOSO/TxNRZ,
TxNEGO, TxCKO.
When bipolar mode is enabled, HDB3/B3ZS encoding is performed over all
transmitted data. In this mode, encoded data is transmitted on TxPOSO (transmit
positive polarity data) and TxNEGO (transmit negative polarity data). When AMI
mode is enabled, data is transmitted without HDB3/B3ZS coding on TxPOSO and
TxNEGO.
When NRZ mode is enabled, TxPOSO/TXNRZ transmits NRZ data, and TxNEGO is
unused.
TxCKO is the clock reference output for TxPOSO/TxNRZ and TxNEGO output pins.
Data outputs are a full-clock period wide and can change on positive or negative
transitions of TxCKO signal.
on the rising edge of TxCKO.
System Signals
The transmit system side interface for each framer consists of TxCKI, TxDATI,
TxGCKO, TxSYNC, TEXTI, and TEXTCKO signals. Each of these pins are
described in
Figure 2-3
parity mode. In this example, ExtFEBE/Cj-bit of Transmitter Overhead Insertion
register is set to 1, and all others are set to 0. In addition to the TEXTI overhead input
and the TxCKI clock input, the response of TEXTCKO clock output is shown for
normal and inverted modes of operation. With these settings, the TEXTCKO clock
Preliminary Information/Mindspeed Proprietary and Confidential
illustrates insertion of FEBE bits through the TEXTI pin in DS3 C-bit
Section
Mindspeed Technologies™
1.2.1.
Figure 2-2
illustrates TxPOSO and TxNEGO changing
Functional Description
500028_016
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