cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 90

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.2.4
2.2.4.1
2-52
PLCP Cell Validation for Receive
In PLCP framed modes, the PLCP receiver processes a serial stream to find PLCP
framing. Octet synchronization is provided externally in DS1 and E1 modes. Internal
or external E3 octet synchronization and DS3 nibble synchronization are provided to
the PLCP framer. Physical layer framing patterns are automatically removed before
recovery of the octet data.
The 57-octet PLCP framing state machine contains three states: in-frame, out-of-
frame, and loss-of-frame. Valid framing is found when two consecutive valid path
overhead octets in sequence are observed after the A1, A2 framing octets. The out-of-
frame state is entered only from the in-frame state, when there are errors in both the
A1 and A2 octets or when there are two consecutive Pn errors. This event is an OOF
event, and is counted. The LOF state is entered after eight consecutive PLCP frames
in the out-of-frame state.
Stuffing and destuffing are provided according to the line type setting in 57-octet
formats. Cycle stuffing is used at the transmit PLCP for DS3 and E3 whenever the
receive PLCP is in the LOF state or Receiver Hold Enable is high, and this function is
enabled with the HldEn bit in PLCPSEL register.
PLCP Status
Errors in either the A1 or A2 PLCP framing octets cause an indication in the
PLCPFrmErr bit in the PLCPSTAT [addr0x04] register. PLCP OOF events are
indicated by the PLCPOOF bit in PLCBSTAT. PLCP LOF events (OOF for eight
consecutive PLCP frames) are indicated by the PLCPLOF bit in PLCBSTAT. Loss of
cell delineation in direct mapped modes (non-PLCP) and in PLCP modes is indicated
by the LOCD bit in the RXCELL [addr 0x2F] register and counted in LOCDCNT
[addr 0x33].
The PLCP Yellow Alarm status bit (PLCPYellow) is set high after 10 consecutive
frames with a PLCP Yellow Alarm value (RAI bit in POH octet G1) of one and
cleared after 10 consecutive frames of a value of zero.
Errors detected in the receiver BIP-8 code checking circuit cause BIP-8 Error
(PLCPBIPErr bit in PLCPSTAT register) to be set and counted (BICNTL/BICNTH
[addr 0x08/0x09] registers). FEBE Error (PLCPFebeErr bit in PLCPSTAT register) is
set if any FEBE-error value (0000 to 1000) is received. This condition is also counted
in the FEBE Error Counter (FEBECNTL/FEBECNTH addr[0x0C/0x0D]). Invalid
FEBE (InvalFEBE bit in PLCBSTAT) is set if any invalid FEBE value (1001 through
1111) is received; a value of 1111 also causes All Ones FEBE (AllOnesFEBE bit in
PLCBSTAT) to be set. This value is used to indicate that the FEBE calculation is not
supported at the far end of the circuit.
Bits 7,6, and 5 in PLCPSTAT register indicated the current state. All other bits are
latched until read and then automatically cleared.
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
When the framing mode is dynamically modified between direct mapping and PLCP
framing, the CX2836x goes into an OOF state. Dynamic switching should only be
used if necessary.
CX28365/6/4 Data Sheet
500028C