cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 132

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x20—RXIDL1 (Receive Idle Cell Header Control Register 1)
RxIdl1[7:0]
0x21—RXIDL2 (Receive Idle Cell Header Control Register 2)
RxIdl2[7:0]
0x22—RXIDL3 (Receive Idle Cell Header Control Register 3)
RxIdl3[7:0]
3-22
RxIdl1[7]
RxIdl2[7]
RxIdl3[7]
7
7
7
RxIdl1[6]
RxIdl2[6]
RxIdl3[6]
These bits hold the Receive Idle cell header for Octet 1 of the incoming cell.
These bits hold the Receive Idle cell header for Octet 2 of the incoming cell.
These bits hold the Receive Idle cell header for Octet 3 of the incoming cell.
6
6
6
The RXIDL1 register contains the first byte of the Receive Idle Cell Header. It defines
ATM idle cells for the cell receiver. Idle cells are discarded from the received stream if
register CVAL (0x0C) bit 6 is set to 1. This header consists of 32 bits divided among
four registers.
Default after reset: 00
The RXIDL2 register contains the second byte of the Receive Idle Cell Header (see
0x20—RXIDL1).
Default after reset: 00
The RXIDL3 register contains the third byte of the Receive Idle Cell Header (see
0x20—RXIDL1).
Default after reset: 00
Preliminary Information/Mindspeed Proprietary and Confidential
RxIdl1[5]
RxIdl2[5]
RxIdl3[5]
5
5
5
Mindspeed Technologies™
RxIdl1[4]
RxIdl2[4]
RxIdl3[4]
4
4
4
RxIdl1[3]
RxIdl2[3]
RxIdl3[3]
3
3
3
RxIdl1[2]
RxIdl2[2]
RxIdl3[2]
2
2
2
RxIdl1[1]
RxIdl2[1]
RxIdl3[1]
1
1
1
CX28365/6/4 Data Sheet
RxIdl1[0]
RxIdl2[0]
RxIdl3[0]
0
0
0
500028C