cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 121

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
3.2
3.2.1
0x04—PMODE (Port Mode Control Register)
PrtMstRst
SrcLoop
FELNLOOP
PhyType[2:0]
500028C
PrtMstRst
7
(1)
(1)
(1)
When written to a logical 1, this bit initiates a Port Master Reset. All cell delineator internal
state machines associated with this port are reset and all cell delineator control registers for
this port, assume their default values.
When written to a logical 1, this bit enables a source loopback. The line transmit clock and
data outputs are connected to the line receive clock and data inputs.
When written to a logical 1, this bit enables the far end line loopback.
These bits determine the Physical Layer Interface mode:
000 = T1 mode
001 = E1 mode
010 = DS3 mode
011 = E3 mode
100 = Reserved, do not use
101 = Reserved, do not use
110 = Reserved, do not use
111 = Power Down
Cell Delineator Registers
Mode Control Registers
—
6
The PMODE register controls the port-level software resets, source loopback, and
physical layer interface mode.
Default after reset: 00
Modification:
Preliminary Information/Mindspeed Proprietary and Confidential
bits 0–2, 4, 5: static
bit 7: dynamic
SrcLoop
5
Mindspeed Technologies™
FELNLOOP
4
—
3
PhyType[2]
2
PhyType[1]
1
PhyType[0]
0
Registers
3
-
11