cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 53

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
2.1.1.4
500028C
Alarm Signal Generation
Each framer is provided with an alarm signal generation mechanism. Some alarms
can be either generated automatically as a reaction to receive conditions, or initiated
by the user (set by bits, inserted via external interface or with the data stream). All
alarm signals initiated by the user are implemented as an activate/deactivate
mechanism in which the user is responsible for activating and deactivating the alarm
signal generation bit. The alarms that can be generated are specified for each available
mode of operation.
For all DS3/E3 modes of operation bits, TxAlm1 and TxAlm0 in the Mode (i) Control
register are responsible for alarm generation.
During alarm generation and transmission, the system interface is not influenced, and
thus, all clocks and signals remain the same.
Loss of Signal Generation
For all modes of operation, the transmit mechanism provides the user with a
programmable option to transmit LOS to the line side by setting bit TxLOS at the
Feature2 Control register. When bit TxLOS is set to 1, the transmit mechanism
generates 0 on the line side data interface outputs (TxPOSO and TxNEGO are
transmitted as 0)—regardless of inserted payload and Overhead bit settings.
DS3 Mode
In DS3 M13/M23 and C-bit parity modes, RAI, AIS, and IDLE alarm signals can be
generated on the outgoing DS3 stream by setting the TxAlm1 and TxAlm0 bit pair in
the Mode (i) Control register for each framer individually.
alarms. In C-bit parity mode, a FEBE alarm is also generated. The various alarms are
described in the following paragraphs.
Table 2-3. DS3 Mode Alarm Signal Setting
Preliminary Information/Mindspeed Proprietary and Confidential
internal FIFO buffer, as specified in
GC (DL)—The general purpose communication channel bytes source is
determined by DLMod[2], DLMod[1], and DLMod[0] at the Transmit Overhead
Insertion 1 Control register together with the NR byte. It can be supplied
externally on the TEXTI pin or transmitted as all 1s (data link disabled). The
framer is also capable of implementing an LAPD data link using an internal FIFO
buffer, as specified in
TxAlm0
Mindspeed Technologies™
0
0
1
1
Section
Bits
2.1.1.6.
TxAlm1
Section
0
1
0
1
2.1.1.6.
Table 2-3
Type Alarm
Normal
summarizes the
Yellow
Functional Description
IDLE
AIS
2
-
15