cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 51

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
500028C
E3–G.832 Mode
E3-G.832 frame structure comprises seven octets of Opportunity bits divided into the
following:
In E3-G.832 mode, the framer provides two options for the insertion of the frame
Opportunity bytes within the data stream: either all frame Overhead bits are inserted
with the data stream (by setting bit ExtDat to 1), or none of the Overhead bits are
inserted via the data stream (setting bit ExtDat to 0).
When the frame Overhead bits are not chosen to be inserted via the data stream, the
following source options are provided for each group of frame Overhead bits:
Preliminary Information/Mindspeed Proprietary and Confidential
implements a LAPD data link with HDLC formatting over the N-bit using an
internal FIFO buffer. For more details about using the data link FIFO buffer, see
Section
Cj-bits—The justification bits are provided either to the transmitter framer with
the data stream, or by the TEXTI external overhead input pin (when ExtFEBE/Cj
is set to 1) when the option of providing them with the data stream is disabled.
FA1 and FA2 (2 octets)
Error Monitoring byte (EM)
Trail Trace byte (TR)
Maintenance and Adaptation byte (MA)
Network operator byte (NR)
General purpose communication channel byte (GC)
FA1 and FA2—The frame alignment bytes that have the value of FA1 = 11110110
(transmitted left to right), FA2 = 00101000 (transmitted left to right) are
automatically inserted by the framer’s transmitter circuit at the beginning of each
frame, or inserted from the TEXTI pin by setting ExtFrm A1 bit.
EM—Error monitoring, BIP-8 byte. When not all overheads are inserted via the
data stream, this byte is generated automatically by the transmitter circuit. The
transmitter calculates a BIP-8 code using even parity. The BIP-8 is calculated over
all bits, including the Overhead bits, from the previous frame. The computed BIP-
8 is placed in the EM byte of the current transmitted E3-G.832 frame.
TR—The trail trace byte to be transmitted can be either supplied externally on the
TEXTI pin (by setting ExtCP/TR bit in the Transmit Overhead Insertion 1 Control
register to 1) or disabled and automatically transmitted as all 0s (by setting ExtCP/
TR bit to 0).
MA RDI—Bit 1 of the MA field is the remote defect indicator. This bit value can
either be generated automatically, controlled by a register or inserted through the
TEXTI pin, depending on AutoRAI, TxAlm, and ExtRAI bit settings. If AutoRAI
= 1, automatic RDI is enabled. In this mode, for as long as Loss of Signal (LOS) or
loss of frame alignment (Out of Frame [OOF]) conditions are detected at the
receiver, the transmitter automatically inserts 1 at the transmitted RDI-bit.
Otherwise, the RDI-bit is transmitted as 0. RDI insertion is also controlled by
TxAlm[1] bit at the Mode Control register. Normally, the transmitter sends 0 as the
RDI-bit. When AutoRAI = 0, setting the ExtRAI bit at the Transmit Overhead
Insertion 2 Control register to 1 causes the RDI-bit insertion through TEXTI pin.
For as long as TxAlm[1] is set to 1, RDI-bit contains 1, regardless of other RDI-bit
sourcing settings.
MA REI—Bit 2 of the MA field is the remote error indication. It can be either
2.1.1.6.
Mindspeed Technologies™
Functional Description
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