cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 160

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
3.4.2
0x29—CR09 (Transmit Overhead Insertion1 Control Register)
DLMod[2:0]
Table 3-10. DS3-C-Bit Parity/E3-G.751 Mode Field Interpretation
3-50
DLMod[2]
DLMod[2]
7
0
1
1
DLMod[1]
Data Link Mode—This field is interpreted differently in different working modes. In E3-G.832
mode, it is a three-bit field that determines the source of NR and GC bytes. In E3-G.751, only
DLMod [2:1] determines the source of the N-bit, while DLMod [0] has no effect. In DS3-C Bit
Parity mode DLMod [2:1] determines the source of the data link (Cb5), and DLMod [0]
determines the source of the reserved C-bits. In DS3-M13/M23, this field has no effect.
Transmitter Registers
6
DLMod[1]
X
0
1
The Transmit Overhead Insertion Control registers CR09 and CR10 are provided to
enable insertion of different overhead fields from these sources:
Default after reset: 00
Direction: Read/Write
Modification: Bits 0–2, 4: static, bits 6–7: dynamic, bit 5: dynamic for DL (G.832)
and static for reserved C-bits (DS3), bit 3: dynamic for Cj and static for FEBE
Tables 3-10
NOTE:
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
Internal automatic generation
Internal registers programmed by the microprocessor
The system via the data stream
The system via TEXTI[11:0] pins
DLMod[0]
5
Transmit Data Link circuit is disabled, and the framer automatically sends the all-1s
pattern on Cb5 bits/N-bit.
Data link data is inserted through the Transmit Data Link FIFO buffer and is processed by
the internal HDLC circuit.
Data link data is inserted through the TEXTI pin and is unaffected by the internal HDLC
circuit.
and
Mindspeed Technologies™
Not all sources are available for every overhead field in every mode. Some control
bits have no effect in a specific mode. Some bits have multiple meanings; it depends
on the working mode.
If the system wants to change the source of the data link (i.e., internal FIFO to TEXTI
pin), it must first disable the data link and then enable it by setting the appropriate
mode. Another example is that when changing the type of byte processed by the
internal HDLC circuit (NR to GC or vice versa) in E3-G.832 mode, the data link must
be disabled first for both (by writing 0 to all three bits).
3-11
AutoRAI
detail the interpretation of this field in the different modes.
4
ExtFEBE/Cj
3
Description
ExtCP/TR
2
ExtFEAC/PD
1
CX28365/6/4 Data Sheet
ExtDat
0
500028C