cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 78

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2-40
These interrupts are independently enabled by setting the RxNFIE, RxMsgIE, and
RxOVRIE fields in the Receive Data Link Control register, and are differentiated by
reading the Status Indication register (Receive Data Link Status register).
The RDL-related status indications available are as follows:
These indications are detected by examining RxNF, RxMsg, RxOVR, RxBlk, and
StatByte fields (respectively) of the Receive Data Link Status register.
Initial Setup
On reset, the RDL is disabled, with no interrupts active. Prior to enabling the RDL, the
desired interrupt enables the Near-Full FIFO threshold, and the RDL-related options
must be set to the desired values through the Receive Data Link and the Receive Data
Link Threshold Control registers. Checking the 16-bit FCS is software-selectable by
setting the RxFCSEn field of the Receive Data Link Control register. If the channel is
functioning in E3-G.832 mode, the NRDL field of the Receive Data Link Control
register should be set to identify which of the two possible overhead bytes (NR or GC)
is processed by the RDL.
Setting the RxDLEn field of the Receive Data link Control register activates the RDL.
Once active, the HDLC-related functionality (flag and abort detection, zero removal)
of the RDL is automatically executed on all DL data flowing through the FIFO buffer.
Once the RDL is enabled, it assumes the channel is idle and starts looking for HDLC
flag sequences.
Preliminary Information/Mindspeed Proprietary and Confidential
Message received:
FIFO overrun:
FIFO near-full (set and cleared with the interrupt)
Message received (set and cleared with the interrupt)
FIFO overrun (set and cleared with the interrupt)
Data block in FIFO buffer (set if there is 1 complete data block in the FIFO
buffer, otherwise cleared)
Type of next FIFO byte (set if status, cleared if data, undefined if the data block in
FIFO indication is not set)
bytes in the remaining incomplete block is again equal to or more than the
threshold, a new interrupt is generated and another type, a2, block terminated).
Turned on when an end-of-message flag sequence or an abort sequence is
detected. A type a1 or b block ends when this interrupt is turned on.
Turned off when the message received status indication is read (unless these
interrupts are promptly and consistently read and cleared, this interrupt means
that one or more message received events have occurred since the last read)
Turned on when the FIFO buffer is full and another byte must be written to it.
A type b block (with overrun error-type) ends when this interrupt is turned on,
and another block of this type is not produced until the interrupt is turned off.
Turned off when there are no more unread complete blocks left in the FIFO
buffer, i.e., when the last byte of the last complete data block has been read
(because all input is discarded by the RDL until the overrun is cleared, this is
the status byte of the incoming message within whose data the overrun error
has occurred).
Mindspeed Technologies™
CX28365/6/4 Data Sheet
500028C