cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 23

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
1.2.1
Table 1-1. Hardware Signal Definition, Microprocessor Interface (1 of 2)
500028C
MReset*
MCLK
MOE*
MCS*
MWR*
MData[7]
MData[6]
MData[5]
MData[4]
MData[3]
MData[2]
MData[1]
MData[0]
MDTACK*
Label
Pin
Master Reset
Microprocessor Clock
Output Enable
Chip Select
Write Strobe
Microprocessor Data
Bus
(LSB)
Data Transfer
Acknowledge
Pin Definitions
Signal
Name
Preliminary Information/Mindspeed Proprietary and Confidential
CX28365
Pin#
A4
D3
G4
G3
H4
G2
H3
C2
E4
E3
F4
F3
F2
J4
Mindspeed Technologies™
CX28366
Pin#
A4
E4
E3
D3
G4
G3
H4
G2
H3
C2
F4
F3
F2
J4
CX28364
Pin#
D3
G4
G3
H4
G2
H3
A4
E4
E3
C2
F4
F3
F2
J4
I/O/Z
O/Z
I/O
I
I
I
I
I
When active (low), all registers and
counters are initialized to their default
values. MReset operates in synchronous
fashion and, therefore, requires that all line
and system clocks are present during the
reset period for a minimum of 30 cycles.
An 8-50 MHz clock signal input. The
microprocessor interface inputs/outputs,
address and data signals are sampled on
the rising edge of this signal. This clock is
also used to sample the input data on the
Programmable InPort1 and InPort2 pins.
Schmitt trigger input.
Enables MData outputs during a read
operation when active low. When high,
MData[7:0] outputs are high impedance.
Active-low enables the read/write decoder.
A high ends the current read or write cycle
and places MData[7:0] outputs in high
impedance.
Used by the microprocessor to indicate a
write cycle if low.
Eight-bit bidirectional bus used for
connecting to a microprocessor system
data bus and transferring data to/from
registers.
Open drain, active low output signifiies in-
progress data transfer cycle. Data-ready
indication for read; transaction-end
indication for write.
Definition
Product Description
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