cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 123

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
3.2.2
0x08—CGEN (Cell Generation Control Register)
DisHEC
EnTxCos
EnTxCellScr
ErrHEC
0x09—HDRFIELD (Header Field Control Register)
InsGFC
InsVPI
InsVCI
500028C
DisHEC
—
7
7
EnTxCos
When written to a logical 1, this bit disables internal generation of the HEC field. When
disabled, the HEC field from the UTOPIA interface remains unchanged in the transmitted cell.
When written to a logical 0, HEC is internally calculated and inserted in the transmitted cell.
When written to a logical 1, this bit enables the Transmit HEC Coset. When written to a
logical 0, the HEC Coset is disabled.
When written to a logical 1, this bit enables the Transmit Cell Scrambler. When written to a
logical 0, the Transmit Cell Scrambler is disabled.
When written to a logical 1, this bit causes the ERRPAT register to be XORed with the
calculated HEC byte for one transmit cell. These bits are cleared automatically by internal
circuitry after the indicated error insertion has taken place. Clearing takes precedence over a
simultaneous write operation to this register.
When written to a logical 1, this bit inserts a Generic Flow Control (GFC) field in the outgoing
header from the TXHDR registers. When written to a logical 0, the GFC field is not changed
prior to transmission.
When written to a logical 1, this bit inserts a Virtual Path Identifier (VPI) field in the outgoing
header from the TXHDR registers. When written to a logical 0, the VPI field is not changed
prior to transmission.
When written to a logical 1, this bit inserts a Virtual Channel Identifier (VCI) field in the
outgoing header from the TXHDR registers. When written to a logical 0, the VCI field is not
changed prior to transmission.
Cell Transmit Registers
—
6
6
This section describes the control registers used for traffic transmission.
The CGEN register controls the device’s cell generation functions.
Default after reset: 60
Modification: dynamic
The HDRFIELD register controls the header insertion elements.
Default after reset: 00
Preliminary Information/Mindspeed Proprietary and Confidential
EnTxCellScr
—
5
5
Mindspeed Technologies™
ErrHEC
InsGFC
4
4
InsVPI
—
3
3
InsVCI
—
2
2
InsPT
1
1
0
InsCLP
0
0
0
Registers
3
-
13