cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 183

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
3.4.9
0x60—Ctr00 (DS3/E3 Parity Error Counter Low)
0x61—Ctr00 (DS3/E3 Parity Error Counter High)
ParCtr[15:0]
500028C
ParCtr[15]
ParCtr[7]
15
7
ParCtr[14]
ParCtr[6]
Parity Error Counter—In DS3 mode, increments for each M-frame where the calculated parity
of the received data bits of the previous M-frame does not match the received parity bits. If the
two parity bits are different, this counter increments. In E3-G.832 mode, it increments for each
frame where the calculated BIP-8 pattern of the received data bits of the previous frame do not
match the received EM byte. The counter increments are per byte, not bits. In E3-G.751 mode,
this counter is not used.
Counters
14
6
There are eight error counters for DS3/E3 errors. All are 16-bit counters except the
LCV counter, which is 24 bits long. The counters indicate 0–65,535 (LCV =
16,777,215) counts of a particular error. If the interrupt for a particular counter is not
enabled, the counter saturates at 65,535 (LCV = 16,777,215). When more than 65,535
(LCV = 16,777,215) counts of that error are received, the saturation indication
appears in the Counter Interrupt Status register. The saturation indication is cleared
when the Counter Interrupt Status register is read. The counter is cleared when the
counter is read.
If the interrupt for a particular counter is enabled in the Interrupt Control register, the
counter does not saturate but rolls over and continue counting from 0. An interrupt is
generated on the MINTR* pin and appears in the Counter Interrupt Status register
when the counter rolls over to a count of 0. The interrupt is cleared when the Counter
Interrupt Status register is read. The counter is cleared when the counter is read. The
counters count according to indications set by the receiver circuit.
All counters are cleared when read by the microprocessor. The interrupt indication for
a particular counter is cleared when the Counter Interrupt Status register is read.
Software should read the low byte first and then the high byte to prevent any missed
counts. All counters are designed so that errors occurring during reads by the
microprocessor are not missed or double-counted.
Value after reset: 00
Direction: Read
Value after enable: 0000
Preliminary Information/Mindspeed Proprietary and Confidential
ParCtr[13]
ParCtr[5]
13
5
Mindspeed Technologies™
ParCtr[12]
ParCtr[4]
12
4
ParCtr[11]
ParCtr[3]
11
3
ParCtr[10]
ParCtr[2]
10
2
ParCtr[1]
ParCtr[9]
1
9
ParCtr[0]
ParCtr[8]
0
8
Registers
3
-
73