28228-12 Mindspeed Technologies, 28228-12 Datasheet
28228-12
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28228-12 Summary of contents
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... PMD Interface or Framer Port 0 Framer (Line) Interface External PMD Line or Interface Framer Port 7 28228-DSH-001-C Host Microprocessor Interface Cell Processor Tx/Rx FIFO G.804 Cell Framer 4 Cells Cell Processor Tx/Rx FIFO G.804 Cell Framer 4 Cells Mindspeed Technologies ™ Mindspeed Proprietary and Confidential Distinguishing Features • 8 cell-based TC Ports • ...
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... Ordering Information Manufacturing Model Number Part Number RS8228EBG 28228-11 RS8228EBGB 28228-12 M28228 28228-21 Revision History Revision Level C — B — A — TM © 2005 Mindspeed Technologies Information in this document is provided in connection with Mindspeed Technologies These materials are provided by Mindspeed as a service to its customers and may be used for informational pur- poses only. Except as provided in Mindspeed’ ...
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... Inserts idle cells when no traffic is ready UTOPIA Level 2 Interface • PHY cell to UTOPIA interface • 50 MHz maximum clock rate • 8/16-bit data path interface 28228-DSH-001-C • Multi-PHY capability Control and Status Microprocessor Interface • Asynchronous SRAM-like interface mode • Synchronous, glueless Bt8233/RS8234 SAR interface mode • ...
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... General Purpose Mode Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.3 UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.3.1 UTOPIA Transmit and Receive FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.3.2 UTOPIA 8-bit and 16-bit Bus Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.3.3 UTOPIA Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.3.4 UTOPIA Multi-PHY Operation .14 2.3.5 UTOPIA Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.3.6 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.4 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.4.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.4.2 Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.4.3 Counters .17 2.4.4 One-second Latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 28228-DSH-001-C Mindspeed Technologies™ Mindspeed Proprietary and Confidential iv ...
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... Idle Cell Mask Control Register .28 0x26—IDLMSK3 (Receive Idle Cell Mask Control Register .28 0x27—IDLMSK4 (Receive Idle Cell Mask Control Register .29 0x28—ENCELLT (Transmit Cell Interrupt Control Register .29 0x29—ENCELLR (Receive Cell Interrupt Control Register .30 28228-DSH-001-C Mindspeed Technologies™ Mindspeed Proprietary and Confidential v ...
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... One-second Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Appendix A:Related Standards Appendix B:Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 B.1 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 B.2 BYPASS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Appendix C:Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 28228-DSH-001-C Octal ATM Transmission Convergence PHY Device Mindspeed Technologies™ Mindspeed Proprietary and Confidential RS8228/M28228 vi ...
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... RS8228 27 mm Mechanical Drawing (Bottom View .20 Figure 4-15. RS8228 27 mm Mechanical Drawing (Top and Side Views .21 Figure 4-16. M28228 17 mm Mechanical Drawing (Bottom View .22 Figure 4-17. M28228 17 mm Mechanical Drawing (Top and Side Views .23 Figure B-2. Test Circuitry Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Figure C-1. Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 28228-DSH-001-C Mindspeed Technologies™ ...
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... UTOPIA Receive Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 4-11. JTAG Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 4-12. One-second Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 4-13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 4-14. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table B-1. Boundary Scan Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 2-3. IEEE Std. 1149.1 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table 2-4. Boundary Scan Register Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 28228-DSH-001-C Mindspeed Technologies™ Mindspeed Proprietary and Confidential viii ...
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... LIU available, or reuse existing devices and software. The RS8228 device provides a low-cost ATM interface architecture for UNI or NNI interfaces. NOTE: Both the 27 mm and 17 mm packages use the same silicon die. All references to the RS8228 apply to the M28228. 1.1 ...
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... M02063 Non-Conformance Figure 1-1. RS8228 Connected to a RS8398 Transceiver UTOPIA ATM Octal ATM Switch Level 2 or SAR Bus Microprocessor Bus 28228-DSH-001-C RS8228 RS8398 Port 0 Port 1 Port 2 Octal T1/E1 PHY Framer Port 3 Port 4 Port 5 Port 6 Port 7 Mindspeed Technologies™ Mindspeed Proprietary and Confidential CX8380 ...
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... Transmit Enable I Transmit Address Bus I I Receive Clock Receive Enable I Receive Address Bus I The overscore on inverted signals in this diagram equates to the “~” in the text of the document. NOTE(S): 28228-DSH-001-C Reset Reset One Second OneSecIn OneSecOut 8kHzIn Interface LTxClk[0] Line Interface LRxClk[0] LTxData[0] ...
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... UTxAddr[0] V LTxSync[0] LRxHld[0] UTxAddr[4] LTxClk[ LTxData[0] UTxData[ UTxAddr[3] Y UTxAddr[2] VGG UTxData[1] The LStatOut pin names list the signal index first [3:0], then the port number [7:0]. NOTE(S): 28228-DSH-001 LStatOut[0][5] LRxData[6] LStatOut[0][6] LRxClk[7] LStatOut[0][ LStatOut[3][7] LStatOut[3][6] ...
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... Table 1-1. RS8228 27 mm Pin Descriptions (1 of 11) Pin Label Signal Name Reset~ Device Reset OneSecIn One-Second Input OneSecOut One-Second Output 8kHzIn One-Second Reference Clock Input 28228-DSH-001-C Driver No. Type I/O Strength D16 TTL — I When asserted low, resets the device. A17 TTL — I When asserted high, the device may latch and hold its status, provided either EnStatLat (bit 5) or EnCntLat (bit 4) in the MODE register (0x0202) are written to a logic 1 ...
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... LRxClk[6] LRxClk[7] LRxData[0] Line Receive Data LRxData[1] Input (ports 0–7) LRxData[2] LRxData[3] LRxData[4] LRxData[5] LRxData[6] LRxData[7] 28228-DSH-001-C Driver No. Type I/O Strength W2 TTL — I Used for the framer (line) transmit timing source. The polarity R3 is set by TxClkPol (bit 3) in the IOMODE register (0x05). ...
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... LInt~[5] LInt~[6] LInt~[7] LStatOut[3][0] Line Status Output 3 LStatOut[3][1] (ports 0-7) LStatOut[3][2] LStatOut[3][3] LStatOut[3][4] LStatOut[3][5] LStatOut[3][6] LStatOut[3][7] 28228-DSH-001-C Driver No. Type I/O Strength T4 TTL — I When transferring framed data, must be connected to the P2 framer’s start-of-frame output. In general purpose mode, this K1 pin is ignored. The polarity is set by RxSyncPol (bit 4) in the G3 IOMODE register (0x05) ...
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... LStatOut[1][2] LStatOut[1][3] LStatOut[1][4] LStatOut[1][5] LStatOut[1][6] LStatOut[1][7] LStatOut[0][0] Line Status Output 0 LStatOut[0][1] (ports 0-7) LStatOut[0][2] LStatOut[0][3] LStatOut[0][4] LStatOut[0][5] LStatOut[0][6] LStatOut[0][7] 28228-DSH-001-C Driver No. Type I/O Strength T3 TTL Reflects various port signals based on the value of StatSel N2 (0x05, bits 0 and 1): J1 LStatOut[3] F3 HECCorr[7: IdleRcvd[7:0] ...
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... MClk Microprocessor Clock B17 MSyncMode Microprocessor Synchronous/ Asynchronous Bus Mode Select MCs~ Microprocessor Chip Select 28228-DSH-001-C Driver No. Type I/O Strength TTL — 8–50 MHz clock signal input. The RS8228 samples the microprocessor interface pins (MCs~, MW/R~, MAs~, MAddr[6:0], and MData[7:0]) on the rising edge of this signal. ...
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... MRd~ Read Control MAs~ Microprocessor Address Strobe or or MWr~ Write Control 28228-DSH-001-C Driver No. Type I/O Strength P17 TTL — I When MSyncMode is asserted high, this pin is a read/write control pin. In this mode, when MW/R~ is asserted high, a write access is enabled and the MData[7:0] pin values will be written to the memory location indicated by the MAddr[6:0] pins ...
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... Bus MData[6] MData[5] MData[4] MData[3] MData[2] MData[1] MData[0] MRdy Microprocessor Ready MInt~ Microprocessor Interrupt Request 28228-DSH-001-C Driver No. Type I/O Strength K20 TTL — I These 13 bits are an address input for identifying the register to access. Registers are mapped into the address space L20 TTL I 0000– ...
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... Clock UTxEnb~ Transmit Enable UTxAddr[0] LSB UTxAddr[1] UTxAddr[2] UTOPIA Transmit Address UTxAddr[3] UTxAddr[4] MSB 28228-DSH-001-C Driver No. Type I/O Strength B15 TTL — I When asserted, the internal boundary-scan logic is reset. This pin has a pull-up resistor. Do not assert this reset unless a clock is provided on TCK. ...
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... Start of Cell UTxClAv UTOPIA Transmit Cell Available URxClk UTOPIA Receive Clock V13 URxEnb~ Receive Enable URxAddr[0] LSB URxAddr[1] URxAddr[2] UTOPIA Receive Address URxAddr[3] URxAddr[4] MSB 28228-DSH-001-C Driver No. Type I/O Strength W5 TTL — I Transmit data from the ATM layer. Y5 TTL I V6 TTL I TTL ...
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... URxData[9] URxData[10] URxData[11] URxData[12] URxData[13] URxData[14] URxData[15] MSB URxPrty UTOPIA Receive Parity URxSOC Receive Start of Cell URxClAv UTOPIA Receive Cell Available 28228-DSH-001-C Driver No. Type I/O Strength Y16 TTL Output the received data to the ATM layer. V15 TTL W16 TTL ...
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... Supply Voltage GND Ground VGG Electrostatic Discharge (ESD) Supply Voltage Test 1 Manufacturing Test 1 Test 2 Manufacturing Test 2 Test 3 Manufacturing Test 3 All input and bi-directional pins have hysteresis. NOTE(S): 28228-DSH-001-C Driver No. Type I/O Strength D6 — — — Power supply connections. D11 D15 F4 F17 K4 L17 ...
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... Pin Diagram and Definitions Figure 1-3 illustrates a pinout diagram for the M28228 single CMOS integrated circuit packaged in a 256-pin BGA. All unused input pins should be connected to ground or power. Unused outputs should be left unconnected. NOTE: The port numbers following the pin names in the Port Interface section represent each of the eight ports as follows: LTxSync[0]— ...
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... LTxSync[4] LTxSync[5] LTxSync[6] LTxSync[7] LRxClk[0] Line Receive Clock LRxClk[1] Input (ports 0–7) LRxClk[2] LRxClk[3] LRxClk[4] LRxClk[5] LRxClk[6] LRxClk[7] 28228-DSH-001-C Driver No. Type I/O Strength C13 TTL — I When asserted low, resets the device. D12 TTL — I When asserted high, the device may latch and hold its status, provided either EnStatLat (bit 5) or EnCntLat (bit 4) in the MODE register (0x0202) are written to a logic 1 ...
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... Line External Framer LCs[1] Chip Select LCs[2] (ports 0-7) LCs[3] LCs[4] LCs[5] LCs[6] LCs[7] LInt*[0] Line Interrupt Request LInt*[1] (ports 0-7) LInt*[2] LInt*[3] LInt*[4] LInt*[5] LInt*[6] LInt*[7] 28228-DSH-001-C Driver No. Type I/O Strength T1 TTL — I Used for serial receive input data TTL — ...
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... LStatOut[1][2] LStatOut[1][3] LStatOut[1][4] LStatOut[1][5] LStatOut[1][6] LStatOut[1][7] LStatOut[0][0] Line Status Output 0 LStatOut[0][1] (ports 0-7) LStatOut[0][2] LStatOut[0][3] LStatOut[0][4] LStatOut[0][5] LStatOut[0][6] LStatOut[0][7] 28228-DSH-001-C Driver No. Type I/O Strength P2 TTL Reflects port signals based on the value of StatSel (bits 0 and the IOMODE register (0x05): H2 LStatOut F2 RcvrHld[7: ...
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... MClk Microprocessor Clock B14 MSyncMode Microprocessor Synchronous/ Asynchronous Bus Mode Select MCs* Microprocessor Chip Select 28228-DSH-001-C Driver No. Type I/O Strength TTL — 8–50 MHz clock signal input. The RS8228 samples the microprocessor interface pins (MCs*, MW/R*, MAs*, MAddr[6:0], and MData[7:0]) on the rising edge of this signal. ...
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... MRd* Read Control MAs* Microprocessor Address Strobe or or MWr* Write Control 28228-DSH-001-C Driver No. Type I/O Strength M14 TTL — I When MSyncMode is asserted high, this pin is a read/write control pin. In this mode, when MW/R* is asserted high, a write access is enabled and the MData[7:0] pin values will be written to the memory location indicated by the MAddr[6:0] pins ...
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... Interrupt Request TRST* Test Reset TCK Test Clock TMS Test Mode Select TDI Test Data Input TDO Test Data Output 28228-DSH-001-C Driver No. Type I/O Strength G16 TTL — I These 13 bits are an address input for identifying the register H15 to access. Registers are mapped into the address space H16 0000– ...
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... UTxData[12] UTxData[13] UTxData[14] UTxData[15] MSB UTxPrty UTOPIA Transmit Parity Input UTxSOC UTOPIA Transmit Start of Cell UTxClAv UTOPIA Transmit Cell Available 28228-DSH-001-C Driver No. Type I/O Strength R10 TTL — clock input used to synchronize transmitted data. T10 TTL — I Enables data transmission when asserted low. ...
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... URxData[11] URxData[12] URxData[13] URxData[14] URxData[15] MSB URxPrty UTOPIA Receive Parity URxSOC Receive Start of Cell URxClAv UTOPIA Receive Cell Available 28228-DSH-001-C Driver No. Type I/O Strength TTL — clock input used to synchronize received data. T11 TTL — I Enables data reception when asserted low. ...
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... Table 1-2. RS8228 17 mm Pin Descriptions (9 of 10) Pin Label Signal Name PWR Supply Voltage 28228-DSH-001-C Driver No. Type I/O Strength D10 — — — Power supply connections E10 E11 F11 G6 G11 G12 H6 H12 J5 J6 J12 K6 K12 L6 L12 L13 M10 M11 ...
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... Pin Label Signal Name GND Ground VGG Electrostatic Discharge (ESD) Supply Voltage Test 1 Manufacturing Test 1 Test 2 Manufacturing Test 2 Test 3 Manufacturing Test 3 All input and bi-directional pins have hysteresis. NOTE(S): 28228-DSH-001-C Driver No. Type I/O Strength F9 — — — Ground connections. F10 G10 H7 H8 ...
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... Block Diagram and Descriptions Figure 1-5 illustrates a detailed block diagram of the RS8228/M28228 device. Traffic is transmitted from the ATM layer device via the UTOPIA bus, in either 16-bit format. The ATM cells are then formatted for serial-line transmission by one of the RS8228 transmit ports. In the receive direction, serial network data is packed into octets by the receive port and passed to the ATM cell receiver module ...
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... TXHDR1–4 registers (0x10–13) and inserted into outgoing cells in place of header bytes received from the ATM layer. Whether the original header cells or replacement cells are sent is controlled by bits 0–4 in the HDRFIELD (0x09) register. 28228-DSH-001-C Mindspeed Technologies™ Mindspeed Proprietary and Confidential ...
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... If any HEC calculation fails in the pre-sync state, the process begins again (see HECs are received. At this time, the “hunt” state is reinitiated. Figure 2-1. Cell Delineation Process Hunt 28228-DSH-001-C Figure 2-1). Synchronization will be held until seven consecutive incorrect 1 Correct HEC Pre-Sync 1 Errored HEC 7 Errored HECs Mindspeed Technologies™ ...
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... Receive Idle Cell Mask Control Registers, IDLMSK1–4 (0x24–27), can be set Don’t Care, causing the corresponding bits of the incoming cell to be treated as matching, regardless of their value. If idle cell rejection is disabled, cells pass directly to user traffic screening. 28228-DSH-001-C Cell Delineation in Sync State No Errors Detected ...
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... SSS scrambling uses the polynomial × can be enabled in EnTxCellScr, bit 5, of the CGEN register (0x08). Descrambling uses the same polynomial to recover the 48-byte cell payload. It can be enabled in EnRxCellScr, bit 4, of the CVAL register (0x0C). SSS scrambling runs Mbps. 28228-DSH-001-C and Table 2-2. ...
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... For the E1 mode, the ATM cells are mapped into time slots 1–15 and 17–31 as described in Recommendation G.704. For the T1 mode, the ATM cells are mapped into time slots 1–24. 28228-DSH-001 polynomial to scramble the entire cell, except the HEC byte. HEC is Figure 2-3. The RS8228 receives a T1/E1 data stream from Mindspeed Technologies™ ...
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... E1 Mod Count 255 T1 Mod Count 192 NOTE(S mode, ATM cells are mapped into time slots 1–15 and 17–31 as described in Recommendation G.704 mode, ATM cells are mapped into time slots 1–24. 28228-DSH-001-C Tx Frame Marker LTxSync Serial Data TPCMI LTxData Rx Frame Marker ...
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... L TxSync must occur at least 10 ns after the rising edge of the 193rd clock must have a minimum of 1 clock period. 2 For T , the hold time after the rising edge of the clock. 3 28228-DSH-001 MSB Octet 1 bit 6 - Octet 1 Mindspeed Technologies™ ...
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... The RS8228 interfaces directly to the Bt8330 DS3 framer, as shown in data stream from the external framer, extracts the ATM cells, ignores the DS3 overhead, and passes the ATM cells to the ATM layer device. The RS8228 performs the inverse process on transmitted data. 28228-DSH-001 ...
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... The RS8228 interfaces directly framer, as illustrated in from the external framer, extracts the ATM cells, ignores the overhead bytes, and passes the ATM cells to the ATM layer device. The RS8228 performs the inverse process on transmitted data. 28228-DSH-001-C Tx Frame Sync TxSYO LTxSync ...
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... ATM cells, ignores the overhead bytes, and passes the ATM cells to the ATM layer device. The RS8228 performs the inverse process on transmitted data. The ATM cell is mapped into bits 1–768 (time slots 1–96) of the 6312 kbps frame. 28228-DSH-001-C Tx Frame Sync LTxSync ...
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... M02063 Non-Conformance Figure 2-8. J2 6312 kbps Diagram JT2F Transmit Framer Receive Framer 768 bits of Payload Clock Tx Serial Data Tx Frame Sync Rx Serial Data Rx Frame Sync 28228-DSH-001-C Tx Frame Sync TCG LTxSync Serial Data LTxData XSD Rx Frame Sync LRxSync RxSYO Serial Data LRxData RTS Clock ...
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... The 1168 kbps limit is imposed by the Bt8970; the RS8228 operates at data rates from 2400 bps to 51 Mbps. (2) LRxSync and LTxSync must be tied to the appropriate voltage level as determined by the value of RxMrkPol and TxMrkPol, bits 6 and 4, in the IOMODE register (0x05). 28228-DSH-001-C Figure Tx Serial Data TSER ...
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... Payload 48 In 16-bit mode, the cells consists of 54 bytes, as listed in The sixth byte, UDF2, is required to maintain alignment but is not read by the RS8228. The remaining bytes are used for payload. 28228-DSH-001-C Table 2-3. The first five bytes are used for header Table 2-4. The first five bytes contain header information. ...
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... To pause the data transfer, UTxEnb~ can be deasserted. To continue the transfer, the controller must reselect the port by transmitting its address one clock cycle before asserting UTxEnb~. The controller must ensure that the cell transfer from this port has been completed, to avoid a start-of-cell error. 28228-DSH-001-C Bit7 ... ...
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... The TxCIAv line will be asserted only if the UTOPIA FIFO has room for at least 2 more cell The TxCIAv line will be asserted only if the UTOPIA FIFO has room for at least 3 more cells The TxCIAv line will be asserted only if the UTOPIC FIFO can accept at least 3 more cells. 28228-DSH-001-C Mindspeed Technologies™ Mindspeed Proprietary and Confidential 2-15 ...
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... Table 2-5. LStatOut Configuration StatSelect LStatOut[3] LStatOut[2] Bit 1 Bit RcvrHld HECCorr 0 1 NonMatch IdleRcvd 28228-DSH-001-C Table 2-5. When the OutStat values (the bottom row of the table) are LStatOut[1] LStatOut[0] HECDet LOCD CellRcvd CellSent Mindspeed Technologies™ Mindspeed Proprietary and Confidential 2.0 Functional Description 2-16 ...
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... When an external framer generates an interrupt, it asserts the associated LInt~ pin. Each LInt~ pin is mapped to a corresponding ExInt bit in the appropriate Port’s SUMINT register and the interrupt is forwarded, as described in Section 2.4.6. 28228-DSH-001-C LStatOut[1] LStatOut[0] SOCErr ParErr ...
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... ENSUMPORT register. The result is ORed to the MInt~ pin (pin B19). The MInt~ pin can be enabled or disabled by setting the EnIntPin (bit 3) in the MODE register (0x202). Figure 2-10 illustrates the flow chart of the interrupt generation process. 28228-DSH-001-C Table 2-6 Chip Select Pin Number ...
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... M02063 Non-Conformance Figure 2-10. Interrupt Indication Flow Chart OneSecInt or ExInt Event Occurs Figure 2-11 illustrates the registers involved in the interrupt generation process. 28228-DSH-001-C TXCELLINT or RXCELLINT Event Occurs Individual No Interrupt Indication Enabled ? Yes Set Individual Interrupt Indication Bit SUMINT No Interrupt Indication Enabled ? Yes Set SUMINT Interrupt Indication Bit ...
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... RXCELLINT (0x002D) LOCDInt 7 HECDetInt 6 HECCorrInt 5 RcvrHldInt 4 OR CellRcvdInt 3 IdleRcvdInt 2 1 NonMatchInt NonZerGFCInt 0 Outputs Enabled by ENCELLR (0x0029) NOTE(S): (1) This interrupt is generated by the associated external framer. 28228-DSH-001-C Port 7 SUMINT (0x01C0) Reserved 7 Reserved 6 Reserved 5 Reserved 4 OR OneSecInt 3 ExInt* 2 TxCellInt 1 RxCellInt 0 Outputs Enabled by ENSUMINT (0x01C1) Port 0 ...
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... RS8228 on that port is also looped back through the Receive Line Interface. Data from the framer interface is ignored. LTxClk, LRxClk, LTxSync, and LRxSync must be present for the loopback mode to function properly for a given port. NOTE: 28228-DSH-001-C Mindspeed Technologies™ Mindspeed Proprietary and Confidential 2-21 ...
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... LTxData LRxClkI LRxSync Loopback TC Receive Port Control LRxData LRxHold This segment is replicated for Ports JTAG Controller TCK TRST~ 28228-DSH-001-C MAddr[12:0] MInt~ Status and Control ATM Cell Transmitter ATM Cell Receiver Cell Cell Validation Alignment VPI/VCI Screening One Second Interface TMS ...
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... Framer 4 Address Range, LCs[4] 1A00–1BFF Framer 5 Address Range, LCs[5] 1C00–1DFF Framer 6 Address Range, LCs[6] 1E00–1FFF Framer 7 Address Range, LCs[7] 28228-DSH-001-C Table 3-1 Table 3-3 lists the port-level control and status registers. All registers Description Mindspeed Technologies™ Mindspeed Proprietary and Confidential ...
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... UTOP2 R/W 0x0F — — 0x10 TXHDR1 R/W 0x11 TXHDR2 R/W 28228-DSH-001-C provide control for the device’s major operating modes, as well as status and OneSec Description Latching — Summary Port Interrupt Status Register — Summary Port Interrupt Control Register — Device Mode Control Register ...
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... R 0x2E TXCELL R 0x2F RXCELL R 0x30 LOCDCNT R 0x31 CORRCNT R 28228-DSH-001-C One-second Description Latching — Transmit Cell Header Control Register 3 — Transmit Cell Header Control Register 4 — Transmit Idle Cell Header Control Register 1 — Transmit Idle Cell Header Control Register 2 — Transmit Idle Cell Header Control Register 3 — ...
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... Input/Output Mode Control Register 0x06 VERSION Part Number/Version Status Register 0x07 OUTSTAT Output Pin Control Register Table 3-5 lists the control registers used for transmission of traffic. 28228-DSH-001-C One-second Description Latching (2) Uncorrected HEC Error Counter — Reserved, set to a logical 0 (2) Transmitted Cell Counter (low byte) ...
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... Receive Idle Cell Header Control Register 3 0x23 RXIDL4 Receive Idle Cell Header Control Register 4 0x24 IDLMSK1 Receive Idle Cell Mask Control Register 1 0x25 IDLMSK2 Receive Idle Cell Mask Control Register 2 28228-DSH-001-C Description Description Mindspeed Technologies™ Mindspeed Proprietary and Confidential Page Number page 13 page 13 page 14 ...
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... Transmit Cell Interrupt Indication Status Register 0x2D RXCELLINT Receive Cell Interrupt Indication Status Register 0x2E TXCELL Transmit Cell Status Register 0x2F RXCELL Receive Cell Status Register 28228-DSH-001-C Description Description Description Mindspeed Technologies™ Mindspeed Proprietary and Confidential 3.0 Registers Page Number page 28 ...
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... Received Cell Counter [Mid Byte] 0x3A RXCNTH Received Cell Counter [High Byte] 0x3C NONCNTL Non-matching Cell Counter [Low Byte] 0x3D NONCNTH Non-matching Cell Counter [High Byte] 28228-DSH-001-C Description Mindspeed Technologies™ Mindspeed Proprietary and Confidential Page Number page 32 page 33 page 33 page 33 ...
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... This bit is a summary indication of any interrupt events that occurred in the indicated registers. This bit is a pointer to the next interrupt indication register to be read. This bit will be cleared when the interrupt bits in the corresponding interrupt indication registers are read and automatically cleared. 28228-DSH-001-C Description Reserved, set to a logical 0. ...
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... EnExtInt 1 1 EnTxCellInt 0 1 EnRxCellInt 28228-DSH-001-C Description Reserved, set to a logical 0. Reserved, set to a logical 0. Reserved, set to a logical 0. Reserved, set to a logical 0. When written to a logical 1, this bit enables the one-second interrupt generated by the OneSecIn pin (pin A17) to appear on the MInt~ output pin (pin B19). ...
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... NOTE(S): (1) These bits should only be changed when the device or port logic reset is asserted. 28228-DSH-001-C Description When written to a logical 1, this bit initiates a Port Master Reset. All internal state machines associated with this port are reset and all control registers for this port, except this one, assume their default values. Only bits 0– ...
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... NOTE(S): (1) These bits should only be changed when the device or port logic reset is asserted. 28228-DSH-001-C Description This bit programs the polarity of the corresponding LRxHld input. Set this bit to 1 for active high input and to 0 for active low input. Tie the LRxHld pin to 3.3 V for default operation. Most systems can ignore this bit and input pin ...
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... Outstat[ Outstat[0] 28228-DSH-001-C Description The part number that uniquely identifies the RS8228 device. The version number that uniquely identifies the specific version of the RS8228 device. Version numbers start at 1 for the first version and are incremented for each revision thereafter. ...
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... InsPT 0 0 InsCLP 28228-DSH-001-C Description When written to a logical 1, this bit disables internal generation of the HEC field. When disabled, the HEC field from the UTOPIA interface remains unchanged in the transmitted cell. When written to a logical 0, HEC is internally calculated and inserted in the transmitted cell. ...
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... ErrPat[ ErrPat[ ErrPat[ ErrPat[0] 28228-DSH-001-C Description These bits hold the Transmit Idle Cell Payload values for outgoing idle cells. Description Error pattern bit 7. Error pattern bit 6. Error pattern bit 5. Error pattern bit 4. Error pattern bit 3. Error pattern bit 2. ...
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... DisCellRcvr 0 0 DisLOCD 28228-DSH-001-C Description When written to a logical 1, this bit enables the Rejection of certain Header cells. When enabled, cells with headers matching the RXHDRx/RXMSKx definition are rejected and all others are accepted. When written to a logical 0, cells with matching headers are accepted and cells with non-matching headers are rejected ...
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... TxFill[0] NOTE(S): (1) These bits should only be changed when the device or port logic reset is asserted. 28228-DSH-001-C Description When written to a logical 1, this bit resets the transmit FIFO pointers. This reset should only be used as a test function because it can create short cells. When written to a logical 1, this bit resets the receive FIFO pointers. This reset should only be used as a test function because it can create short cells ...
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... TxHdr1[ TxHdr1[0] 28228-DSH-001-C Description This is a test function, set to a logical 0. This is a test function, set to a logical 0. When written to a logical 1, this bit disables UTOPIA outputs for this port. These bits are the Multi-PHY Device Address. Each RS8228 port should have a unique address ...
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... TxHdr3[ TxHdr3[ TxHdr3[0] 28228-DSH-001-C Description These bits hold the Transmit Header values for Octet 2 of the outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09). VPI bits VCI bits Description These bits hold the Transmit Header values for Octet 3 of the outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09) ...
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... TxIdl1[ TxIdl1[ TxIdl1[0] 28228-DSH-001-C Description These bits hold the Transmit Header values for Octet 4 of the outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09). VCI bits Payload-type bits Cell Loss Priority bit Description These bits hold the Transmit Idle Cell Header values for Octet 1 of the outgoing cell. ...
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... TxIdl3[ TxIdl3[0] 28228-DSH-001-C Description These bits hold the Transmit Idle Cell Header values for Octet 2 of the outgoing cell. VPI bits VCI bits Description These bits hold the Transmit Idle Cell Header values for Octet 3 of the outgoing cell. ...
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... RxHdr1[ RxHdr1[ RxHdr1[0] 28228-DSH-001-C Description These bits hold the Transmit Idle Cell Header values for Octet 4 of the outgoing cell. VCI bits Payload-type bits Cell Loss Priority bit Description These bits hold the Receive Header values for Octet 1 of the incoming cell. ...
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... RxHdr3[ RxHdr3[ RxHdr3[0] 28228-DSH-001-C Description These bits hold the Receive Header values for Octet 2 of the incoming cell. Description These bits hold the Receive Header values for Octet 3 of the incoming cell. Mindspeed Technologies™ Mindspeed Proprietary and Confidential 3 ...
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... RxMsk1[ RxMsk1[ RxMsk1[0] 28228-DSH-001-C Description These bits hold the Receive Header values for Octet 4 of the incoming cell. Section Description These bits hold the Receive Header Mask for Octet 1 of the incoming cell. Mindspeed Technologies™ Mindspeed Proprietary and Confidential 2 ...
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... RxMsk3[ RxMsk3[ RxMsk3[0] 28228-DSH-001-C Description These bits hold the Receive Header Mask for Octet 2 of the incoming cell. Description These bits hold the Receive Header Mask for Octet 3 of the incoming cell. Mindspeed Technologies™ Mindspeed Proprietary and Confidential 3 ...
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... RxIdl1[ RxIdl1[0] 28228-DSH-001-C Description These bits hold the Receive Header Mask for Octet 4 of the incoming cell. Description These bits hold the Receive Idle cell header for Octet 1 of the incoming cell. Mindspeed Technologies™ Mindspeed Proprietary and Confidential ...
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... RxIdl3[ RxIdl3[0] 28228-DSH-001-C Description These bits hold the Receive Idle cell header for Octet 2 of the incoming cell. Description These bits hold the Receive Idle cell header for Octet 3 of the incoming cell. Mindspeed Technologies™ Mindspeed Proprietary and Confidential 3 ...
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... IdlMsk1[ IdlMsk1[0] 28228-DSH-001-C Description These bits hold the Receive Idle cell header for Octet 4 of the incoming cell. Description These bits hold the Receive Idle cell header mask for Octet 1 of the incoming cell. Mindspeed Technologies™ Mindspeed Proprietary and Confidential Section 2 ...
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... IdlMsk3[ IdlMsk3[0] 28228-DSH-001-C Description These bits hold the Receive Idle cell header mask for Octet 2 of the incoming cell. Description These bits hold the Receive Idle cell header mask for Octet 3 of the incoming cell. Mindspeed Technologies™ Mindspeed Proprietary and Confidential 3 ...
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... Description These bits hold the Receive Idle cell header mask for Octet 4 of the incoming cell. Description When written to a logical 1, this bit enables the Parity Error Interrupt. When written to a logical 1, this bit enables the Start of Cell Error Interrupt. ...
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... Single event— transition on the corresponding status bit causes this interrupt to occur, provided that this interrupt has been enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt. 28228-DSH-001-C Description When written to a logical 1, this bit enables a Loss of Cell Delineation Interrupt. ...
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... NOTE(S): (1) This status indicates an event that occurred since the register was last read. 28228-DSH-001-C Description When a logical 1 is read, this bit indicates that a Loss of Cell Delineation has occurred. When a logical 1 is read, this bit indicates that a HEC Error was detected. ...
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... LOCDCnt[1] 0 — LOCDCnt[0] 28228-DSH-001-C Description When a logical 1 is read, this bit indicates a Loss of Cell Delineation. When a logical 1 is read, this bit indicates that an uncorrected HEC Error was detected. When a logical 1 is read, this bit indicates that a HEC Error was corrected. ...
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... TxCnt[2] 1 — TxCnt[1] 0 — TxCnt[0] 28228-DSH-001-C Description Corrected HEC Error counter bit 7 (MSB). Corrected HEC Error counter bit 6. Corrected HEC Error counter bit 5. Corrected HEC Error counter bit 4. Corrected HEC Error counter bit 3. Corrected HEC Error counter bit 2. Corrected HEC Error counter bit 1. ...
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... RxCnt[3] 2 — RxCnt[2] 1 — RxCnt[1] 0 — RxCnt[0] 28228-DSH-001-C Description Transmitted cell counter bit 15. Transmitted cell counter bit 14. Transmitted cell counter bit 13. Transmitted cell counter bit 12. Transmitted cell counter bit 11. Transmitted cell counter bit 10. Transmitted cell counter bit 9. Transmitted cell counter bit 8. ...
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... NonCnt[3] 2 — NonCnt[2] 1 — NonCnt[1] 0 — NonCnt[0] 28228-DSH-001-C Description Received cell counter bit 15. Received cell counter bit 14. Received cell counter bit 13. Received cell counter bit 12. Received cell counter bit 11. Received cell counter bit 10. Received cell counter bit 9. Received cell counter bit 8. ...
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... NOTE(S): (1) This bit is a pointer to the next interrupt indication register to be read. This bit is cleared when the interrupt bit in the corresponding interrupt indication register is read and automatically cleared. 28228-DSH-001-C Description Non-matching cell counter bit 15 (MSB). Non-matching cell counter bit 14. Non-matching cell counter bit 13. ...
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... UtopMode 1 1 Handshake 0 0 BusWidth 28228-DSH-001-C Section 2.4.6. Description This bit enables PortInt[7] to appear on the MInt~ pin (pin B19). This bit enables PortInt[6] to appear on the MInt~ pin (pin B19). This bit enables PortInt[5] to appear on the MInt~ pin (pin B19). This bit enables PortInt[4] to appear on the MInt~ pin (pin B19). ...
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... Timing Diagram Nomenclature ( Symbol Timing Relationship t Pulse Width pw t Pulse Width High pwh t Pulse Width Low pwl t Setup Time s t Setup High Time sh 28228-DSH-001-C Specifications Input Input Input Data Clock Data Clock Mindspeed Technologies™ Mindspeed Proprietary and Confidential Table 4-1 lists the Waveform 4-1 ...
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... Hold High Time hh t Hold Low Time hl t Propagation Delay pd t Propagation Delay—High-to-Low pdhl t Propagation Delay—Low-to-High pdlh t Enable Time en 28228-DSH-001-C Data Clock Clock Data Clock Data Clock Data Input Output Input Output Input Output Input Output Mindspeed Technologies™ ...
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... Period per t Cycle Time cyc f Maximum Frequency max f Minimum Frequency min Figure 4-1 and Figure 4-2 illustrate how input and output waveforms are defined. 28228-DSH-001-C 4.0 Electrical and Mechanical Specifications Input Output Input Output Input Output Input Output Input Output Async Input Clock Input Mindspeed Technologies™ ...
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... M02063 Non-Conformance Figure 4-1. Input Waveform t rise Figure 4-2. Output Waveform 4.1.1 Microprocessor Timing Figures 4-3 through 4-6 and Tables 4-2 microprocessor interface. 28228-DSH-001-C t fall t per t t fall rise t pwl t pwh t per through 4-5 show the timing requirements and characteristics of the Mindspeed Technologies™ Mindspeed Proprietary and Confidential 2 ...
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... Propagation Delay, MData[7:0] from the falling edge of pd (MCs~ + MRd~) t Disable, MData[7:0] from the rising edge of (MCs~ + MRd~) dis t Enable, MRdy from the falling edge of (MCs~ + MRd~) enzl t Disable, MRdy from the rising edge of (MCs~ + MRd~) dislz 28228-DSH-001 pwl dis ...
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... Setup, MData[7:0] from the falling edge of (MCs~ + MWr Hold, MData[6:0] from the rising edge of (MCs~ + MWr Enable, MRdy from the falling edge of (MCs~ + MRd~) enzl t Disable, MRdy from the rising edge of (MCs~ + MRd~) dislz 28228-DSH-001 pwl t enzl t dislz Description Mindspeed Technologies™ ...
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... Figure 4-5. Microprocessor Timing Diagram—Synchronous Read MCs~ MW/R~ t MAs~ MAddr[6:0] t pwh Mclk MData[7:0] MRdy t enzl2 MInt~ MSyncMode (high) 28228-DSH-001 pwl per enzl1 dislz1 Mindspeed Technologies™ Mindspeed Proprietary and Confidential 4 ...
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... Enable, MRdy from the rising edge of MClk enzl1 t Disable, MRdy from the falling edge of MClk dislz1 t Enable, MInt~ from the rising edge of MClk enzl2 t Disable, MInt~ from the rising edge of MClk dislz2 28228-DSH-001-C Description Mindspeed Technologies™ Mindspeed Proprietary and Confidential Min Max Unit ...
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... Figure 4-6. Microprocessor Timing Diagram—Synchronous Write MCs~ MW/R~ MAs~ MAddr[6:0] MData[7:0] t pwh Mclk MRdy MInt~ MSyncMode (high) 28228-DSH-001 per pwl t t enzl1 dislz Mindspeed Technologies™ Mindspeed Proprietary and Confidential 4 ...
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... Tables 4-6 (Line) interface. The LCS uses combinational logic and is functional even when the RS825X is in reset. NOTE: Figure 4-7. Framer (Line) Control Timing Diagram Lint~ t pwh MClk LCs 28228-DSH-001-C Description through 4-8 show the timing requirements and characteristics of the Framer ...
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... Period, LTxClk (Min MHz, Max. at 1.54 MHz) per t Setup, LTxSync to the rising edge of LTxClk s t Hold, LTxSync from the rising edge of LTxClk h t Propagation Delay, LTxData from the rising edge of LTxClk pd 28228-DSH-001-C 4.0 Electrical and Mechanical Specifications Description pwl ...
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... Hold, LRxHld from the rising edge of LRxClk h1 t Setup, LRxData to the rising edge of LRxClk s2 t Hold, LRxData from the rising edge of LRxClk h2 t Setup, LRxSync to the rising edge of LRxClk s3 t Hold, LRxSync from the rising edge of LRxClk h3 28228-DSH-001 ...
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... UTOPIA Interface Timing Figures 4-10 through 4-11 and Tables 4-9 UTOPIA interface. Figure 4-10. UTOPIA Transmit Timing Diagram UTxEnb~ UTxAddr[4:0] UTxData[15:0] UTxPrty UTxSOC UTxClk UTxClAv 28228-DSH-001-C 4.0 Electrical and Mechanical Specifications through 4-10 show the timing requirements and characteristics of the ...
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... Hold, UTxSOC from the rising edge of UTxClk h5 t Enable, UTxClAv from the rising edge of UTxClk en t Propagation Delay, UTxClAv from the rising edge of UTxClk pd t Disable, UTxClAv from the rising edge of UTxClk dis 28228-DSH-001-C Description Mindspeed Technologies™ Mindspeed Proprietary and Confidential Min Max Unit 8 — — ...
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... Hold, URxEnb~ from the rising edge of URxClk h1 t Setup, URxAddr to the rising edge of URxClk s2 t Hold, URxAddr from the rising edge of URxClk h2 t Enable, URxData[15:0] from the rising edge of URxClk en1 28228-DSH-001-C 4.0 Electrical and Mechanical Specifications pwl t t per ...
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... Disable, URxClAv from the rising edge of URxClk dis4 4.1.4 JTAG Interface Timing Figure 4-12 and Table 4-11 show the timing requirements and characteristics of the JTAG interface. Figure 4-12. JTAG Timing Diagram t rec TRST~ TMS TDI t pwh TCK TDO 28228-DSH-001-C Description pwl per Mindspeed Technologies™ ...
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... Disable, TDO from the falling edge of TRST~ dis2 4.1.5 One-second Interface Timing Figure 4-13 and Table 4-12 show the timing requirements and characteristics of the one-second interface. Figure 4-13. One-second Timing Diagram OneSecIn t pwh1 OneSecClk OneSecOut 28228-DSH-001-C 4.0 Electrical and Mechanical Specifications Description t t pwh2 pwl2 t t pwl1 per t pd Mindspeed Technologies™ ...
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... Junction Temperature Maximum Current at Maximum Clock Frequencies (not including LStatOut outputs) Static Discharge Voltage Latch-up Current DC Input Current θ JC θ JA 28228-DSH-001-C Description indicate the maximum stresses that the RS8228 can tolerate without Value –0.5 to +3.3 V –0.5 to Vdd + 0.5 V –0.5 to Vdd + 0.5 V ° ° –40 ...
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... Bidirectional Capacitance Power consumed when processing cells on all 8 ports simultaneously data rate DS3 data rate 4 Mechanical Drawing The RS8228 is a 272-ball BGA package. A mechanical drawing of the device is provided in Figure 4-15. 28228-DSH-001-C 4.0 Electrical and Mechanical Specifications Min Typical 3.0 3.3 0 — 0.7*VDD — ...
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... M02063 Non-Conformance Figure 4-14. RS8228 27 mm Mechanical Drawing (Bottom View 1.27 0.76 1.44 REF 28228-DSH-001 1.44 REF 1.27 BOTTOM VIEW (272 SOLDER BALLS) Mindspeed Technologies™ Mindspeed Proprietary and Confidential A1 BALL PAD CORNER ...
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... Figure 4-15. RS8228 27 mm Mechanical Drawing (Top and Side Views) 27.00 15.00 A1 Ball End Corner A1 Ball Pad Indicator, 1.0 Dia. Optional 7 45° Chamfer 4 Places TOP VIEW 28228-DSH-001 Package 0.20 (4X) X +0.70 –0.05 +0.70 24.00 –0.00 Mindspeed Technologies™ Mindspeed Proprietary and Confidential 4.0 Electrical and Mechanical Specifications 0. 0. ...
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... M02063 Non-Conformance 4 Mechanical Drawing The M28228 is a 256-ball BGA package. A mechanical drawing of the device is provided in Figure 4-17. Figure 4-16. M28228 17 mm Mechanical Drawing (Bottom View) 1.00 1.00 REF 28228-DSH-001 (256 SOLDER BALLS) A1 BALL PAD CORNER 1.00 REF 1.00 Mindspeed Technologies™ ...
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... Figure 4-17. M28228 17 mm Mechanical Drawing (Top and Side Views) 17.00 15.00 A1 Ball End Corner A1 Ball Pad Indicator, 1.0 Dia. Optional 7 45° Chamfer 4 Places TOP VIEW A1 ball pad corner I.D. for plate mold marked by ink. 7 Auto mold: dimple to be formed by mold cap. Primary Datum Z and seating plane are defined by the spherical 6 crowns of the solder balls ...
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... Vintage Park Drive Foster City, CA 94404-1138 For ITU documents contact: Omnicom Phillips Business Information 1201 Seven Locks Road, Suite 300 Potomac, MD 20854 1-800 OMNICOM (666-4266) 28228-DSH-001-C PCI Special Interest Group P.O. Box 14070 Portland, OR 97214 1-800-433-5177 1-503-797-4207 ANSI 11 West 42nd Street ...
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... Serial Test Data Input The test circuitry includes the Boundary Scan Register, a BYPASS Register, an Instruction Register, and the Test Access Port (TAP) controller (see Figure 28228-DSH-001-C I/O I When at a logic low, this signal asynchronously resets the boundary scan test circuitry and puts the test controller into the reset state. This state allows normal system operation ...
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... Boundary Scan Register 1-bit Bypass Register 2 0 3-bit Instruction Register Instruction EXTEST SAMPLE/PRELOAD Private Private Private Private Private BYPASS Mindspeed Technologies™ Mindspeed Proprietary and Confidential TDO Register Accessed ...
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... LCs[6] 15 LInt~[5] 16 (1) 17 LCs[5] 18 LInt~[4] 19 (1) 20 LCs[4] 21 LInt~[3] 22 (1) 23 LCs[3] 24 LInt~[2] 28228-DSH-001-C Cell Type Controlling Cell controlr — output3 — input — input — input — input — input — controlr — output3 7 input — controlr — ...
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... MAddr[12] 44 MAddr[11] 45 MAddr[10] 46 MAddr[9] 47 MAddr[8] 48 MAddr[7] 49 MAddr[6] 50 MAddr[5] 51 MAddr[4] 52 MAddr[3] 53 MAddr[2] 54 MAddr[1] 55 MAddr[0] 56 MAs~,MWr~ 57 MCs~ 28228-DSH-001-C Cell Type Controlling Cell controlr — output3 25 input — controlr — output3 28 input — controlr — output3 31 controlr — bidir 33 bidir 33 bidir 33 bidir 33 bidir ...
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... URxData[7] 77 URxData[6] 78 URxData[5] 79 (1) 80 URxData[4] 81 URxData[3] 82 URxData[2] 83 URxData[1] 84 (1) 85 URxData[0] 86 (1) 87 URxPrty 88 (1) 89 URxSOC 90 (1) 28228-DSH-001-C Cell Type Controlling Cell input — controlr — output3 59 input — input — input — input — input — output3 69 output3 69 output3 69 controlr — output3 69 ...
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... UTxData[2] 114 UTxData[1] 115 UTxData[0] 116 UTxAddr[4] 117 UTxAddr[3] 118 UTxAddr[2] 119 UTxAddr[1] 120 UTxAddr[0] 121 LTxClk[0] 122 LTxSync[0] 123 (1) 28228-DSH-001-C Cell Type Controlling Cell output3 90 input — input — input — input — input — controlr — output3 97 input — ...
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... LTxClk[2] 148 LTxSync[2] 149 (1) 150 LTxData[2] 151 LRxClk[2] 152 LRxData[2] 153 LRxSync[2] 154 LRxHld[2] 155 LStatOut[3][2] 156 LStatOut[2][2] 28228-DSH-001-C Cell Type Controlling Cell output3 123 input — input — input — input — output3 132 output3 132 output3 132 controlr — ...
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... LRxHld[4] 181 LStatOut[3][4] 182 LStatOut[2][4] 183 LStatOut[1][4] 184 (1) 185 LStatOut[0][4] 186 LTxClk[5] 187 LTxSync[5] 188 (1) 189 LTxData[5] 28228-DSH-001-C Cell Type Controlling Cell output3 158 controlr — output3 158 input — input — controlr — output3 162 input — input — ...
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... LTxSync[7] 214 (1) 215 LTxData[7] 216 LRxClk[7] 217 LRxData[7] 218 LRxSync[7] 219 LRxHld[7] 220 LStatOut[3][7] 221 LStatOut[2][7] 222 LStatOut[1][7] 28228-DSH-001-C Cell Type Controlling Cell input — input — input — input — output3 197 output3 197 output3 197 controlr — output3 — ...
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... Related Pin Name 223 (1) 224 LStatOut[0][7] 225 Test[1] 226 Test[2] 227 Test[3] NOTE(S): (1) See IEEE Std. 1149.1b-1994, Table B.4, for more information on cell types. 28228-DSH-001-C Cell Type Controlling Cell controlr — output3 223 input — input — input — Mindspeed Technologies™ ...
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... Device Master Reset Device Logic Reset Enable Status Latching Enable Counter Latching Port Master Reset Receiver Hold Polarity Receiver Sync Polarity Receiver Clock Polarity Transmitter Sync Polarity 28228-DSH-001-C General Use Control Registers Device Mode Control Register MODE (0x0202) page ...
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... Idle Cell Payload[6] Idle Cell Payload[5] Idle Cell Payload[4] Error Pattern[7] Error Pattern[6] Error Pattern[5] Error Pattern[4] Transmit Header[7] Transmit Header[6] Transmit Header[5] Transmit Header[4] 28228-DSH-001-C Cell Transmit Control Registers Cell Generation Control Register CGEN (0x08 page 13 ...
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... Receive Header Mask[5] Receive Header Mask[4] Receive Idle Cell Header[7] Receive Idle Cell Header[6] Receive Idle Cell Header[5] Receive Idle Cell Header[4] 28228-DSH-001-C Cell Transmit Control Registers (Continued) Transmit Idle Cell Header Control Register 1–4 TXIDL1–4 (0x14–17 ...
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... Receive Idle Cell Mask[5] Receive Idle Cell Mask[4] UTOPIA Receiver Disable Multi-PHY Address[4] Port[7] Summary Port[6] Summary Port[5] Summary Port[4] Summary 28228-DSH-001-C Cell Receive Control Registers (Continued) Receive Idle Cell Mask Control Register 1–4 IDLMSK1–4 (0x24–27 ...
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... Enable Transmit FIFO Overflow Interrupt Enable Receive FIFO Overflow Interrupt Enable Loss of Cell Delineation Interrupt Enable HEC Error Detected Interrupt Enable HEC Error Corrected Interrupt Enable Receiver Hold Interrupt 28228-DSH-001-C Status and Interrupt Registers (Continued) Summary Port Interrupt Control Register ENSUMPORT (0x0201 ...
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... Loss of Cell Delineation Interrupt HEC Error Detect Interrupt HEC Error Correct Interrupt Receiver Hold Interrupt LOCD Event Counter[7] LOCD Event Counter[6] LOCD Event Counter[5] LOCD Event Counter[4] 28228-DSH-001-C Status and Interrupt Registers (Continued) Transmit Cell Interrupt Indication Status Register TXCELLINT (0x2C ...
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... Uncorrected HEC Error Counter[5] Uncorrected HEC Error Counter[4] Transmitted Cell Counter[7] Transmitted Cell Counter[6] Transmitted Cell Counter[5] Transmitted Cell Counter[4] Transmitted Cell Counter[15] Transmitted Cell Counter[14] Transmitted Cell Counter[13] Transmitted Cell Counter[12] 28228-DSH-001-C Counters (Continued) Corrected HEC Error Counter CORRCNT (0x31 ...
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... Received Cell Counter[13] Received Cell Counter[12] Non-matching Cell Counter[7] Non-matching Cell Counter[6] Non-matching Cell Counter[5] Non-matching Cell Counter[4] Non-matching Cell Counter[15] Non-matching Cell Counter[14] Non-matching Cell Counter[13] Non-matching Cell Counter[12] 28228-DSH-001-C Counters (Continued) Received Cell Counter (Low Byte) RXCNTL (0x38 ...
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General Information: (949) 579-3000 Headquarters - Newport Beach 4000 MacArthur Blvd., East Tower Newport Beach, CA. 92660 ...