cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 151

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
CbitP/832
0x21—CR01 (Counter Interrupt Control Register)
EXZCtrIE
XDgrCtrlE
LCVCtrIE
FEBECtrIE
PthCtrlE
FerrCtrIE
PDgrCtrIE
ParCtrIE
500028C
EXZCtrlE
7
XDgrCtrlE
C-Bit Parity/E3-G.832 Mode—Selects which type of framing is present on the transmitted
DS3/E3 signal.
Excessive Zeros Counter Interrupt Enable—A control bit that allows interrupts from the DS3/
E3 EXZ Counter to appear on MINTR* pin.
X-bits Disagreement Counter Interrupt Enable—A control bit that allows interrupts from the
DS3/Disagreement Counter to appear on MINTR* pin.
Line Code Violation Counter Interrupt Enable—A control bit that allows interrupts from the
DS3/E3LCV Counter to appear on MINTR* pin.
FEBE Event Counter Interrupt Enable—A control bit that allows interrupts from the DS3
FEBE/E3-G.832 REI Event Counter to appear on MINTR* pin.
Path Parity Error Counter Interrupt Enable—A control bit that allows interrupts from the Path
Parity Error Counter to appear on MINTR* pin.
Frame Error Counter Interrupt Enable—A control bit that allows interrupts from the Frame
Error Counter to appear on MINTR* pin.
Disagreement Counter Interrupt Enable—A control bit that allows interrupts from the DS3 P
Disagreement Counters to appear on the MINTR* output pin.
Parity Error Counter Interrupt Enable—A control bit that allows interrupts from the DS3
Parity/E3-G.832 BIP-8 Error Counter to appear on MINTR* pin.
6
The Counter Interrupt Control register is provided to enable or disable individual
interrupt sources. To enable an interrupt for a particular counter, the control bit
corresponding to that counter must be set high in the Interrupt Control register. This
enables the interrupt from that source to be asserted on the MINTR* output pin. If a
counter has its interrupt control bit set low, interrupts from this counter are masked
from asserting on MINTR*.
Default after reset: 00
Direction: Read/Write
Modification: Dynamic
E3Frm
0
0
1
1
Preliminary Information/Mindspeed Proprietary and Confidential
LCVCtrIE
5
Mindspeed Technologies™
FEBECtrIE
4
CbitP/832
0
1
0
1
PthCtrIE
3
Framing Mode
DS3-M13/M23
DS3-C-Bit Parity
E3-G.751
E3-G.832
FerrCtrIE
2
PDgrCtrIE
1
ParCtrIE
0
Registers
3
-
41