cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 158

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x28—CR08 (Feature5 Control Register)
RxAutoAll1
RefrmStp
RxAIS
RxAll1
RxOvhMrk
3-48
RxAutoAll1
7
RefrmStp
Receive Automatic All 1s—Set to enable automatic generation of an all-1s stream on RXDAT
pin in response to a fault detection. When set and a LOS, OOF, AIS, or Idle are detected in
DS3 mode or LOS, OOF, or AIS are detected in E3 mode, the data received on RXPOS,
RXNEG is presented to the receiver circuit, but is not present on RXDAT pin. It is overwritten
by an all-1s stream. The assertion of all 1s continues as long as one or more of these conditions
is valid. When clear, all-1s sequence on RXDAT pin occurs due to RxAll1 bit in this register.
RxAll1 and RxAIS bits have precedence over the RxAutoAll1 bit.
Reframe Mechanism Stop—This bit controls the behavior of the frame-search mechanism.
When this bit is set, no frame-search is conducted regardless of OOF status. When it has been
cleared, frame-search resumes shifted forward by one bit from the current frame position, until
a new frame is located. When it is cleared, searching occurs in response to an OOF status.
Receive Data Stream AIS—When set, enables driving of an AIS pattern in all DS3 and E3
modes on RXDAT pin. Data received on RXPOS, RXNEG is presented to the receiver circuit
but is not present on RXDAT pin. Detection and the count of errors, alarms, and events
continue while this mode operates. When cleared, data received on RXPOS, RXNEG, and
processed by the receiver circuit is present on RXDAT pin. If both RxAll1 and RxAIS are
active, a data stream of all 1s is generated.
Receive Data Stream is All 1s—When set, enables driving an all-1s stream on RXDAT pin.
Data received on RXPOS, RXNEG is presented to the receiver circuit, but is not present on
RXDAT pin. Detection and the count of errors, alarms, and events continue while this mode
operates. When cleared, the data received on RXPOS, RXNEG, and processed by the receiver
circuit is present on RXDAT pin. If both RxAll1 and RxAIS are active, data stream of all 1s is
generated.
Receive Overhead Bits Mark—This bit controls behavior of the RxSYNC pin. When set,
RxSYNC marks the bit positions of all Opportunity bits. When cleared, RxSYNC marks the
beginning of a new frame.
6
Default after rest: 00
Direction: Read/Write
Modification: Bits 0–3: static, bits 4–6: dynamic, bit 7: static
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
RxAIS
5
Mindspeed Technologies™
To produce a forced reframe, the microprocessor usually needs two write cycles, the
first to write 1 to the bit, and then to write 0 to it.
RXAll1
4
RxOvhMrk
3
2
0
RxInvClk
1
CX28365/6/4 Data Sheet
LRxCkRis
0
500028C