cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 103

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
2.5
2.5.1
Figure 2-20. Source Loopback Diagram
500028C
LRxSync
LRxData
LTxSync
Interface
LTxData
LRxClk
LTxClk
Framer
(Line)
This segment is replicated for Ports 0–11
Loopback
Control
Loopback
Cell Delineator Source Loopback
There are two source loopback mechanisms in the CX2836x device, one in the cell
delineators and one in the framers.
For the Cell Delineator loopback, the Source loopback checks that the host (the ATM
layer) is communicating with the PHY. It is enabled and disabled in bit 5 of the
PMODE register (0x04). When the Source loopback is enabled for a given port, all
data transmitted by the CX2836x on that port is also looped back through the Receive
Line interface. Data from the Framer interface is ignored.
NOTE:
TCK
Preliminary Information/Mindspeed Proprietary and Confidential
TRST~
JTAG Controller
Transmitter
Receiver
Line
Line
TMS
TDI
Mindspeed Technologies™
LTxClk, LRxClk, LTxSync, and LRxSync must be present for the Loopback mode to
function properly for a given port.
TDO
Alignment
Status and Control
Cell
ATM Cell Transmitter
ATM Cell Receiver
VPI/VCI Screening
Cell Validation
8kHzIn
One Second Interface
OneSecIn
Microprocessor
Interface
4-cell
FIFO
4-cell
FIFO
OneSecOut
Interface
Interface
Transmit
UTOPIA
UTOPIA
Receive
Level 2
Level 2
Host
Host
Functional Description
UTOPIA
Level 2
Interface
UTxClk
UTxClav
UTxEnb~
UTxSOC
UTxData[15:0]
UTxPrty
UTxAddr[4:0]
URxClk
URxClav
URxEnb~
URxSOC
URxData[15:0]
URxPrty
URxAddr[4:0]
500028_037
2
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