cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 111

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

3.1
500028C
Register Map
3.0 Registers
The CX2836x registers control and observe the device’s operations. Registers are of
three types: Control, Status, and Counters. Control registers are used for
configuration. Status registers report events such as alarms and errors. Counters count
events and performance errors in the received signal and data path. Counters are
automatically cleared when read.
Some Control registers can be modified whether a port is disabled or enabled
(dynamic modification). Some Control registers can only be modified when a port is
disabled (static modification). When a register with mixed bits (both dynamic and
static bits in the same register) is modified while a port is enabled, the software may
modify the dynamic bits, but must leave the static bits unchanged.
Data Link static (DL-static) bits can be modified dynamically only if the internal data
link mechanism is disabled:
The register map contains the following groups of register addresses:
The CD, PLCP, and framer register groups each include sets of registers which are
replicated for each of twelve ports. To determine the exact address of a specific
register, add the register group base address to the register offset address (all numbers
are hexadecimal). For example:
For the Cell Delineator Port 3, IOMODE register (from
Common Registers (in
considered global. The External Chip Select addresses are defined in
are applicable if OUTPORT2 pins are configured to output Line Chip Select signals.
LCS*[n] is activated when the address bus, MAddr[13:0], is within the address range
Preliminary Information/Mindspeed Proprietary and Confidential
Rx bits: when the RxDLEn field in the Receive Data Link Control register is
cleared
Tx bits: when the DLMod fields in the Transmit Overhead Insertion Control
register is set, so that HDLC and FIFO mechanism is disabled and does not affect
the DL channel
Cell Delineator (CD) registers
PLCP Registers
Framer Registers
Common Registers
External Chip Select Addresses
0x00C0 (port 3 base address) + 0x05 (IOMODE register offset address) =
0x00C5 (exact register address)
Mindspeed Technologies™
(Tables 3-3
(Tables 3-5
Table
(Table
3-7) are not associated with a specific port and are
3-7)
and 3-4)
and 3-7)
(Tables 3-1
(Table
3-8)
and 3-2)
Table 3-1
and
Table Table
Table 3-8
and
3-2):
3
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1