cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 140

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
0x2E—TXCELL (Transmit Cell Status Register)
ParErr
SOCErr
TxOvfl
RxOvfl
CellSent
BusCnflct
DisTxIdle
3-30
ParErr
(1)
(1)
(1)
(1)
7
(1)
(1)
When a logical 1 is read, this bit indicates that a parity error was received on the transmit
UTOPIA input data octet.
When a logical 1 is read, this bit indicates that a Start of Cell Error was received on the
UTxSOC pin (pin W12).
When a logical 1 is read, this bit indicates that a Transmit FIFO Overflow condition occurred
in the transmit UTOPIA FIFO.
When a logical 1 is read, this bit indicates that a Receive FIFO Overflow condition occurred in
the receive UTOPIA FIFO.
When a logical 1 is read, this bit indicates that a non-idle cell was formatted and transmitted.
When a logical 1 is read, this bit indicates that a UTOPIA bus conflict has occurred, which
means that a duplicate multi-PHY address has been programmed for this port. Check the
contents of the UTOP2 register (0x0E).
When written to 1, this bit enables the last cell value transmitted prior to an idle period to be
output repeatedly until new data is available (the last value replaces what would be idle cells).
When set to 0 (default), idle cells are transmitted when there is a gap in the data stream.
SOCErr
6
The TXCELL register contains status for the cell transmitter.
Default after reset: DisTxIdle set to 0
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
TxOvfl
5
Mindspeed Technologies™
(1)
This status shows an event that has occurred since the register was last read.
RxOvfl
4
CellSent
3
BusCnflct
2
—
1
CX28365/6/4 Data Sheet
DisTxIdle
0
500028C