cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 82

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.1.2.6
2-44
Far-End Alarm and Control Channel Reception
The FEAC channel resides on the C13 bit of DS3 C-bit Parity frames. There are three
ways to access FEAC contents: 1. through the data stream (marked with other
overheads by RxGCKO), 2. through the data stream marked by REXTCKO, 3.
through a register-based microprocessor interface.
two; this section describes the third.
FEAC messages are in the form of 16-bit code words, with a pattern of
0xxxxxx011111111 (right-to-left). The code word overhead are the 10 fixed bits. The
code word proper are the six x bits. The entire 16 bits are represented as the complete
code word pattern. When no alarm or control signal is present, the channel carries an
all-1s (idle) pattern. Internal circuitry (Receive FEAC [RFEAC] block) provides logic
and a register for implementing FEAC message identification. As this channel is
undefined in DS3 M13/M23 and E3 modes, the RFEAC is automatically disabled in
these modes.
The RFEAC comes in two modes (selectable through the FEACSin field of the
Feature3 Control register), 1. single code word detection (makes no assumptions
about FEAC messages repetitions) 2. multiple code word detection (assumes each
FEAC message is repeated at least 10 times).
In single code word detection, a valid code word is detected when one complete code
word pattern is located.
In multiple code word detection, a valid code word is detected when nine complete
code word patterns with the same code word proper are located, using the following
algorithm F:
F1. [Initiation]
F2. [Tentative]
F3. [Tentative and Alternative]
F4. [Alternative]
F5. [Possible Termination]
Preliminary Information/Mindspeed Proprietary and Confidential
Locate a complete code word pattern, store its code word proper (cp1) in a 6-bit
register (termed the tentative code word), set a 4-bit counter to 1, and go to step
F2.
Locate another complete code word pattern and compare its code word proper
(cp2) with the tentative code word:
Locate another complete code word pattern and compare its code word proper
(cp3) with the tentative code word:
Compare cp3 with the alternative code word:
If counter 9 declare a valid code word and end algorithm, if not go to step F2.
a.
b.
a.
b.
a.
b.
If identical, add 1 to the counter, and go to step F5
If not, store cp2 in another 6-bit register (termed the alternative code word)
and go to step F3.
If identical, add 2 to the counter (for cp2 and cp3), and go to step F5
If not, go to step F4.
If identical, store the alternative code word in the tentative code word register,
set the counter to 2 (for cp2 and cp3) and return to step F2
If not, store the alternative code word in the tentative code word register, set
the counter to 1, store cp3 in the alternative code word register, and return to
step F3.
Mindspeed Technologies™
Section 2.1.2.3
discusses the first
CX28365/6/4 Data Sheet
500028C