cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 159

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
RxInvClk
LRxCkRis
500028C
Receive System Side Inverted Clocks—This bit controls the polarity of RxGCKO and
REXTCKO output clocks. When the bit is cleared, RxGCKO and REXTCKO rising edges are
in parallel to the data change on RXDAT pin. In this mode, both clock gaps are active low.
When this bit is set, RxGCKO and REXTCKO are inverted. The RxGCKO and REXTCKO
falling edges are in parallel to the data change on RxDATO pin. In this mode, both clock gaps
are active high.
LIU Receive Clock Polarity Control—Used to define the RxCKI edge upon which the receiver
input data on RxPOSI, RxNEGI pins are clocked out by the LIU. When set, data are sampled
by the device on the falling edge of RxCKI, therefore it is clocked out by the LIU on the rising
edge of RxCKI. When clear, data are sampled by the chip on the rising edge of RxCKI,
therefore it is clocked out by the LIU on the falling edge of RxCKI.
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
Registers
3
-
49