UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 980

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

the IICn register and the transmitting side cancels the wait state when data is written to the IICn register.
978
A wait state may be automatically generated depending on the setting of the IICCn.WTIMn bit.
Normally, the receiving side cancels the wait state when the IICCn.WRELn bit is set to 1 or when FFH is written to
The master device can also cancel the wait state via either of the following methods.
• By setting the IICCn.STTn bit to 1
• By setting the IICCn.SPTn bit to 1
Transfer lines
Remark
Master
Slave
ACKEn
SDA0n
SCL0n
SCL0n
SCL0n
IICn
IICn
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
(b) When master and slave devices are both in a nine-clock wait state
(master: transmission, slave: reception, and ACKEn bit = 1)
H
Generate according to previously set ACKEn bit value
D2
6
6
D1
7
7
Figure 20-14. Wait State (2/2)
Master and slave both wait
after output of ninth clock.
User’s Manual U19601EJ2V0UD
CHAPTER 20 I
D0
8
8
ACK
9
9
Wait state
from master/
slave
2
C BUS
IICn data write (cancel wait state)
1
Wait state
from slave
D7
FFH is written to IICn register
or WRELn bit is set to 1.
1
D6
2
2
D5
3
3