UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 775
UPD70F3786GJ-GAE-AX
Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3786GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
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16.7.5 Reception error
are a parity error, framing error, and overrun error. In the FIFO mode (UBnFIC0.UBnMOD bit = 1), the three types of
errors that can occur during a receive operation are a parity error, framing error, and overflow error.
error, framing error, or overrun error occurs in the single mode. The UBnSTR.UBnOVF bit is set to 1 if an overflow
error occurs in the FIFO mode. The UBnRXAP.UBnPEF or UBnRXAP.UBnFEF bit is set to 1 if a parity error or framing
error occurs in the FIFO mode. At the same time, a reception error interrupt request signal (INTUBnTIRE) occurs.
The contents of the error can be detected by reading the contents of the UBnSTR or UBnRXAP register.
or the UBnCTL0.UBnPWR or UBnCTL0.UBnRXE bit. The contents of the UBnRXAP register are reset when 0 is
written to the UBnCTL0.UBnPWR bit.
Remark
UBnPE
UBnFE
UBnOVE
UBnOVF
UBnPEF
UBnFEF
In the single mode (UBnFIC0.UBnMOD bit = 0), the three types of errors that can occur during a receive operation
As a result of data reception, the UBnSTR.UBnPE, UBnSTR.UBnFE, or UBnSTR.UBnOVE bit is set to 1 if a parity
The contents of the UBnSTR register are reset when 0 is written to the UBnOVF, UBnPE, UBnFE, or UBnOVE bit,
Error Flag
n = 0, 1
Single mode
FIFO mode
Valid Operation
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
Mode
UBnPE
UBnFE
UBnOVE
UBnOVF
UBnPEF
UBnFEF
Error Flag
Table 16-5. Reception Error Causes
User’s Manual U19601EJ2V0UD
Parity error
Overrun error
Overflow error
Parity error
Framing error
Framing error
Reception Error
The parity specification during transmission does
not match the parity of the receive data
No stop bit detected
The reception of the next data is ended before
data is read from the UBnRX register
The reception of the next data is ended while
receive FIFO is full and before data is read.
The parity specification during transmission does
not match the parity of the data to be received.
The stop bit is not detected when the target data
is loaded.
Cause
773
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