UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1464

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1462
14
13
12
11
10
9
8
7
6
(18) RXSTATUS: Reception status interrupt register
Bit
This register stores the cumulative result of the reception status. If an interrupt source that is not masked by
the setting of the RXSTATUS_MASK register has been generated, the INTETMRS interrupt is generated. The
INTETMRS interrupt signal is kept asserted while any bit of this register is set.
If an interrupt source masked by the RXSTATUS_MASK register has been generated, the corresponding bit of
this register is set as well.
This register is not affected by the setting of RXERSEL (receive error selection register).
All the bits of the RXSTATUS register are cleared when the register is read.
Access
Address
Default value 0000 0000H. This register is cleared to its default value by all types of resets.
Cautions 1. The reception status interrupt status register is cleared when it is read.
RLENE
VLAN
USOP
RPCF
RCFR
DBNB
RLOR
RLER
RCRCE
RLER
31
23
15
Name
R
R
R
R
0
0
0
7
2. Be sure to set bits 31 to 15 to “0”.
recommended to copy interrupt sources to variables so that several interrupt sources
that are generated at the same time can be detected.
This register is read-only, in 32-bit units.
002E 0260H
RCRCE
RLENE
Receive packet length error
This bit indicates that the received packet is less than 64 bytes or greater than 1,518 bytes (less
than 64 bytes or greater than 1,522 bytes in the case of a VLAN packet).
VLAN packet reception
A packet whose TPID field matches VLTP has been received
A control packet with an undefined opcode has been received
A pause control packet received
A control packet has been received
A packet containing dribble nibble has been received.
The length field is greater than 1,500.
The length field does not match the data field length
A receive CRC error occurred.
30
22
14
R
R
R
R
0
0
6
RXER
CHAPTER 23 ETHERNET CONTROLLER
VLAN
29
21
13
R
R
R
R
0
0
5
User’s Manual U19601EJ2V0UD
USOP
CEPS
28
20
12
R
R
R
R
0
0
4
Note 2
Note 2
.
.
RPCF
REPS
27
19
11
R
R
R
R
0
0
3
Description
Notes 3, 4
RCFR
PAIG
26
18
10
R
R
R
R
0
0
2
.
Note 1
Note 2
.
.
DBNB
TXRX
25
17
R
R
R
R
0
0
9
1
RLOR
DVCF
24
16
R
R
R
R
0
0
8
0
(1/2)
It is