UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 951

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

I
(1) IIC shift register n (IICn)
(2) Slave address register n (SVAn)
(3) SO latch
(4) Wakeup controller
(5) Prescaler
(6) Serial clock counter
2
C0n includes the following hardware.
The IICn register converts 8-bit serial data into 8-bit parallel data and vice versa, and can be used for both
transmission and reception.
Write and read operations to the IICn register are used to control the actual transmit and receive operations.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
The SVAn register sets local addresses when in slave mode.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
The SO latch is used to retain the output level of the SDA0n pin.
This circuit generates an interrupt request signal (INTIICn) when the address value set to the SVAn register
matches the received address or when an extension code is received.
This selects the sampling clock to be used.
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to
verify that 8-bit data was transmitted or received.
Remark
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
Registers
Control registers
Item
Table 20-1. Configuration of I
IIC shift register n (IICn)
Slave address register n (SVAn)
IIC control register n (IICCn)
IIC status register n (IICSn)
IIC flag register n (IICF0n)
IIC clock select register n (IICCLn)
IIC function expansion register n (IICXn)
IIC division clock select registers 0 to 2 (OCKS0 to OCKS2)
User’s Manual U19601EJ2V0UD
CHAPTER 20 I
2
C BUS
Configuration
2
C0n
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