UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1497

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 23 ETHERNET CONTROLLER
(2) Procedure for transmitting or receiving a serial management frame
Serial management frames are transmitted or received as follows.
First, the MIND.SCANA bit is checked to see whether the SCAN command is under execution.
If not, the MIND.BUSY bit is checked to see whether the serial management frame is being accessed. If the
BUSY bit is 1, the Ethernet controller waits until it is cleared to 0. On the other hand, while the SCAN
command is being executed, the MCMD.SCANC bit is cleared to 0 and then the Ethernet controller waits until
the BUSY bit is cleared to 0.
Next, the address of the external PHY device to which the frame is to be transmitted and the address of a
register in the PHY device are set to the MADR.FIAD and RGAD bits, respectively.
When a write access is to be made, writing is started by writing data to the MWTD.CTLD bits.
The BUSY bit is set to 1 when data has been written to the MWDT register and cleared to 0 when writing is
complete.
A read access is started by writing 1 to the MCMD.RSTAT bit. When the RSTAT bit is set to 1, the BUSY bit is
set to 1. The BUSY bit is cleared to 0 after completion of reading. The host system can obtain the data of the
PHY register by confirming that the BUSY bit is 0 and then reading the MRDD.PRSD bit.
To execute the SCAN command, set the MCMD.SCANC bit to 1. When this bit has been set to 1, reading is
repeatedly executed. The MIND.SCANA bit is set to 1 while the SCAN command is being executed. The
MIND.NVALID bit is set to 1 until the first read access is completed after the SCAN command has been
executed. The MIND.BUSY bit is set to 1 when the SCAN command is executed. If the SCAN command is
disabled (by clearing the MCMD.SCANC bit to 0), the MIND.BUSY bit is cleared to 0 after the current read
access is completed.
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User’s Manual U19601EJ2V0UD