UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 328

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

326
(i) Operation to write 0 (without conflict with setting)
(ii) Operation to write 0 (conflict with setting)
(2) Operation timing in pulse width measurement mode
(a) Clearing overflow flag
(TAAnOVF bit)
(TAAnOVF bit)
Overflow flag
Overflow flag
0 write signal
0 write signal
The overflow flag can be cleared to 0 by clearing the TAAnOVF bit to 0 with the CLR instruction and by
writing 8-bit data (bit 0 is 0) to the TAAnOPT0 register. To accurately detect an overflow, read the
TAAnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
Remark
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of the
overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no
overflow has occurred even when an overflow has actually occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is
cleared to 0 with the CLR instruction, the overflow flag remains set (1) even after execution of the clear
instruction.
set signal
set signal
Overflow
Overflow
n = 0 to 5
L
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
User’s Manual U19601EJ2V0UD
(iii) Operation to clear to 0 (without conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
(TAAnOVF bit)
(TAAnOVF bit)
access signal
access signal
Overflow flag
Overflow flag
0 write signal
0 write signal
set signal
set signal
Overflow
Overflow
Register
Register
L
H
Read
Read
Write
Write