UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1169

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note Check the MUC and DN bits using one read access.
Remarks 1. Check the MBON bit at the start and end of the interrupt routine to see if the message buffer and
2. If the ROVF bit has been once set (1), the receive history list contradicts. Therefore, scan all the
receive history register can be accessed, because a CAN sleep mode transition request which
has been held pending may be under execution. If the MBON bit is cleared (0), stop the
processing under execution. Re-execute the processing after the MBON bit is set (1) again. It is
therefore recommended to cancel the CAN sleep mode transition request before executing
reception interrupt servicing.
receive message buffers that have completed reception.
Figure 21-50. Reception via Interrupt (Using C0RGPT Register)
END
Yes
CHAPTER 21 CAN CONTROLLER
Read C0MDATAxm,
C0MDLCm, C0MIDLm,
and C0MIDHm registers.
Read C0RGPT register.
User’s Manual U19601EJ2V0UD
Receive completion
Clear ROVF bit = 1
Read normal data.
Clear ROVF bit.
Clear DN bit = 1
MUC bit = 0
ROVF bit = 1?
RHPM bit = 1?
Clear DN bit.
DN bit = 0
interrupt
START
AND
Yes
Yes
No
Note
No
No
Read illegal data.
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