UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 781

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
(4) Allowable baud rate range during reception
Maximum allowable
Minimum allowable
The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception
is shown below.
Caution The equations described below should be used to set the baud rate error during reception
As shown in Figure 16-11, after the start bit is detected, the receive data latch timing is determined according
to the counter that was set by the UBnCTL2 register. If all data up to the final data (stop bit) is in time for this
latch timing, the data can be received normally.
Applying this to 11-bit reception is, theoretically, as follows.
Remark
FL = (Brate)
Minimum allowable value:
Brate: UARTBn baud rate
k:
FL:
Latch timing margin: 2 clocks
UARTBn
so that it always is within the allowable error range.
n = 0, 1
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
value
value
UBnCTL2 set value
1-bit data length
1
Figure 16-11. Allowable Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
FLmin
Bit 0
User’s Manual U19601EJ2V0UD
Bit 0
=
Bit 0
FL
11
×
FL
Bit 1
Bit 1
Bit 1
k
1 data frame (11 × FL)
2
k
FLmin
2
FLmax
×
FL
Bit 7
=
Bit 7
Bit 7
21
Parity bit
k
2
Parity bit
k
+
2
Parity bit
FL
Stop bit
Stop bit
Stop bit
779

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