UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1465

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
5
4
3
2
1
0
Bit
Notes 1. This bit is not set to 1 if a CRC error or RXER has occurred.
RXER
CEPS
REPS
PAIG
TXRX
DVCF
2. This bit is not set to 1 if a CRC error has occurred.
3. This bit is not set to 1 if the MACC1.FLCHT bit is 0.
4. RLOR is set to 1 and RLER is not set to 1 if the length field exceeds 1,500.
5. This bit indicates that one of the events has occurred between when the reception status was
6. A packet in which these events have occurred is ignored and not transferred to the upstream
Name
updated previously and when it is updated this time.
system.
RXER has been detected.
A false carrier has been detected
A packet of preamble + SFD or a packet whose data field ends with 1 nibble has been received
5, 6
This bit indicates that any of the following events has occurred after the previous reception
• A carrier length exceeding 6,072 nibbles (3,036 bytes) has been detected.
• The next packet with IFG + preamble + SFD has been received before the time required to
• An illegal preamble or SFD has been received when the MACC1.PUREP bit is set.
Transmission is started (collision occurs) during half-duplex reception (immediately after reception
has been started).
The received packet is a valid control packet (that does not contain an error).
.
transmit 80 bits has elapsed after a packet has been received.
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD
Note 5
.
Description
Note 5
.
(2/2)
Notes
1463

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