UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 253

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(12) Noise elimination control register (TANFCn)
Digital noise elimination can be selected for the TIAAn0 and TIAAn1 pins. The noise elimination setting is
selected using the TANFCn register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among
f
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution Time equal to the sampling clock × 3 clocks is required until the digital noise eliminator is
Remark
XX
and f
(n = 0 to 5)
TANFCn
XX
After reset: 00H
/4. Sampling is performed 3 times.
initialized after the sampling clock has been changed. If the valid edge of TIAAn0 and
TIAAn1 is input after the sampling clock has been changed and before the time of the
sampling clock × 3 clocks passes, therefore, an interrupt request signal may be generated.
Therefore, when using the external trigger function, the external event function, and the
capture trigger function of TAAn, enable TAAn operation after the time of the sampling clock
× 3 clocks has elapsed.
n = 0 to 5
Remarks 1. Since sampling is performed 3 times, the noise width for reliably eliminating
TANFENn
TANFENn
TANFCn0
< >
0
1
0
1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Does not perform digital noise elimination
Performs digital noise elimination
2. In the case of noise with a width smaller than 2 sampling clocks, an
f
f
R/W
XX
XX
/4
noise is 2 sampling clocks.
interrupt request signal is generated if noise synchronized with the
sampling clock is input.
0
Address: TANFC0 FFFFF5A0H, TANFC1 FFFFF5A2H,
User’s Manual U19601EJ2V0UD
0
TANFC2 FFFFF5A4H, TANFC3 FFFFF5A6H,
TANFC4 FFFFF5A8H, TANFC5 FFFFF5AAH
Setting of digital noise elimination
0
Digital sampling clock
0
0
0
TANFCn0
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