UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1443

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
23.4.3 FIFO controller control registers
31
30
27 to 24
(1) MFFCONT: FIFO controller control register
Cautions 1. Be sure to set the following bits to the values specified below (fixed values). If other values
Bit
Access
Address
Default value 0000 0000H. This register is cleared to its default value by all types of resets.
LOOPBACK
RXSDMA1 RXSDMA0
LOOPBACK
RCSEL
IMLP[3:0]
2. Be sure to set bits 29, 28, 23 to 19, 13, and 7 to 3 to “0”.
R/W
R/W
31
23
15
Name
are set, the correct operation cannot be guaranteed.
• RXSDMA[1:0] = 10
• ASOE = 0
• APS = 1
• APL = 1
• RXTHRC = 0
• TXTHRC = 0
R
R
0
7
0
This register can be read and written in 32-bit units.
002E 0200H
RCSEL
Loopback mode
Loopback between the transmit FIFO and receive FIFO is performed.
RXCLK selection
TXCLK is selected to be internally connected, instead of RXCLK.
Set this bit if it is necessary to change RXCLK to TXCLK when the MAC and the FIFO controller
are in the loopback mode.
Set these bits to “0000”.
R/W
R/W
0: Normal mode
1: Loopback mode
0: Normal mode
1: Clock switch mode (RXCLK switched to TXCLK)
30
22
14
R
R
0
6
0
CHAPTER 23 ETHERNET CONTROLLER
29
21
13
R
R
R
R
0
0
5
0
0
User’s Manual U19601EJ2V0UD
ASOE
R/W
28
20
12
R
R
R
0
0
4
0
IMLP3
APS
R/W
R/W
27
19
11
R
R
0
3
0
Description
FLOWCNT
IMLP2
TABT
R/W
R/W
APL
R/W
R/W
26
18
10
2
IVPAUSE ZEROPAUSE
RXTHRC
TXTHRC
IMLP1
R/W
R/W
R/W
R/W
25
17
9
1
IMLP0
RXEN
TXEN
R/W
R/W
R/W
R/W
24
16
8
0
(1/2)
1441

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