UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 890

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.8 Cautions
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Cautions concerning CSIEn are shown below (n = 0, 1).
(1) Stopping CSIEn
(2) Enabling transfer
(3) Caution on CEnCTL0 register setting
(4) Writing data to CEnTX0 register in single mode
(5) CEnSTR register status in continuous mode
The CSIEn unit is reset and CSIEn is stopped when the CEnCTL0.CEnPWR bit is cleared to 0. To operate
CSIEn, first set the CEnPWR bit to 1.
Usually, before clearing the CEnPWR bit to 0, clear both the CEnTXE and CEnRXE bits to 0 (after the end of
transfer).
Be sure to write 1 to the CEnSTR.CEnPCT bit to clear all the CSIBUFn pointers to 0 before enabling transfer
by setting the CEnCTL0.CEnPWR bits to 1. If the CEnTXE or CEnRXE bit is set to 1 without clearing the
pointers, and if the previously transferred data remains in the CSIBUFn register, transferring that data is
immediately started.
If transfer data is set to the CSIBUFn register before transfer is enabled, transfer is started as soon as the
CEnTXE or CEnRXE bit is set to 1.
Be sure to set the port pins related to the CSIEn function to the alternate-function mode before using CSIEn.
Then set the CEnPWR bit to 1 before setting the other bits.
Be sure to confirm that the CEnSTR.CEnFLF register is 0 when writing data to the CEnTX0 register. Even if
data is written to this register when the CEnFLF bit is 1, the CSIBUFn overflow interrupt (INTCEnTIOF) is
issued, and the written data is ignored.
The CEnSTR register is in the same status when transfer data is written (before start of transfer) after the
CSIBUFn pointer is cleared (CEnSTR.CEnPCT bit = 1) and when 16 data have been transferred
(CEnSTR.CEnFLF bit = 0, CEnSTR.CEnEMF bit = 1, CEnSTR.CEnSFP3 to CEnSTR.CEnSFP0 bits = 0000).
CHAPTER 18 CLOCKED SERIAL INTERFACE E WITH FIFO (CSIE)
User’s Manual U19601EJ2V0UD