UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 879

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(11) Transmission mode
(12) Reception mode
(13) Transmission/reception mode
The transmission mode is set when the CEnCTL0.CEnTXE bit is set to 1 and the CEnRXE bit is cleared to 0.
In this mode, transmission is started by a trigger that writes transmit data to the CEnTX0 register or sets the
CEnTXE bit to 1 when transmit data is in the CSIBUFn register (n = 0, 1). The value input to the SIEn pin
during transmission is latched in the shift register (SIOn) but is not transferred to the CEnRX0 and CSIBUFn
registers at the end of transmission.
The transmission/reception completion interrupt (INTCEnT) occurs immediately after data is sent out from the
SIOn register.
The reception mode is set when the CEnCTL0.CEnTXE bit is cleared to 0 and the CEnCTL0.CEnRXE bit is
set to 1. In this mode, reception is started by using the processing of writing dummy data to the CEnTX0
register as a trigger (n = 0, 1). In the single mode (CEnCTL0.CEnTMS bit = 1), however, the condition of
starting reception includes that the receive data has been transferred from the SIOn register to the CEnRX0
register. (If reception to the SIOn register is completed when the previous receive data is held in the CEnRX0
register without being read, the receive data stored in the SIOn register is transferred to the CEnRX0 register
by reading the CEnRX0 register.) In the continuous mode, reception starts by writing dummy data of the
number of receive data to the CEnTX0 register with the first dummy data write processing taken as a trigger.
The SOEn pin outputs a low level.
The transmission/reception completion interrupt (INTCEnT) occurs immediately after receive data is
transferred from the SIOn register to the CEnRX0 register.
The transmission/reception mode is set when both the CEnCTL0.CEnTXE bit = 1 and the CEnCTL0.CEnRXE
bit = 1. In this mode, transmission/reception is started by using the processing to write transmit data to the
CEnTX0 register as a trigger (n = 0, 1). In the single mode (CEnCTL0.CEnTMS bit = 0), however, the
condition of starting transmission/reception includes that the receive data has been transferred from the SIOn
register to the CEnRX0 register. (If reception to the SIOn register is completed when the previously received
data is held in the CEnRX0 register without being read, the receive data stored in the SIOn register is
transferred to the CEnRX0 register by reading the CEnRX0 register.)
CHAPTER 18 CLOCKED SERIAL INTERFACE E WITH FIFO (CSIE)
User’s Manual U19601EJ2V0UD
877