UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1018

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.16.3 Slave operation
(processing requiring a significant change of the operation status, such as stop condition detection during
communication) is necessary.
that the INTIICn interrupt servicing performs only status change processing and that the actual data communication is
performed during the main processing.
these flags to the main processing instead of the INTIICn signal.
(1) Communication mode flag
(2) Ready flag
(3) Communication direction flag
1016
The following shows the processing procedure of slave operation.
Basically, the operation of the slave device is event-driven.
The following description assumes that data communication does not support extension codes. Also, it is assumed
Therefore, the following three flags are prepared so that the data transfer processing can be performed by passing
This flag indicates the following communication statuses.
Clear mode:
Communication mode: Data communication in progress (valid address detection stop condition detection, ACK
This flag indicates that data communication is enabled. This is the same status as an INTIICn interrupt during
normal data transfer. This flag is set in the interrupt processing block and cleared in the main processing block.
The ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is
transmitted without clear processing (the address match is regarded as a request for the next data).
This flag indicates the direction of communication and is the same as the value of IICSn.TRCn bit.
Remark
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
I
2
C
Figure 20-21. Overview of Software During Slave Operation
Data communication not in progress
from master not detected, address mismatch)
INTIICn signal
Setting, etc.
User’s Manual U19601EJ2V0UD
CHAPTER 20 I
Interrupt servicing
Setting, etc.
Data
2
C BUS
Therefore, processing by an INTIICn interrupt
Flag
Main processing