UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 795

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.10 Cautions
Cautions concerning UARTBn are shown below.
(1) When supply clock to UARTBn is stopped
(2) Caution on setting UBnCTL0 register
(3) Caution on setting UBnFIC2 register
(4) Transmission interrupt request signal
(5) Initialization during continuous transmission in single mode
(6) Initialization during continuous transmission (pending mode) in FIFO mode
(7) Initialization during continuous transmission (pointer mode) in FIFO mode
When the supply of clocks to UARTBn is stopped (for example, IDLE and STOP modes), operation stops with
each register retaining the value it had immediately before the supply of clocks was stopped. The TXDBn pin
output also holds and outputs the value it had immediately before the supply of clocks was stopped.
However, operation is not guaranteed after the supply of clocks is restarted. Therefore, after the supply of
clocks is restarted, the circuits should be initialized by setting the UBnPWR bit = 0, UBnRXE bit = 0, and
UBnTXE bit = 0.
• When using UARTBn, set the external pins related to the UARTBn function to the alternate function and
• Be sure to input a high level to the RXDBn pin when setting the external pins related to the UARTBn
Be sure to clear the UBnCTL0.UBnTXE bit (to disable transmission) and UBnCTL0.UBnRXE bit (to disable
reception) to 0 before writing data to the UBnFIC2 register. If data is written to the UBnFIC2 register with the
UBnTXE or UBnRXE bit set to 1, the operation is not guaranteed.
In the single mode, the transmission enable interrupt request signal (INTUBnTIT) occurs when the UBnTX
register becomes empty (when 1 byte of data is transferred from the UBnTX register to the transmit shift
register). In the FIFO mode, the FIFO transmission end interrupt request signal (INTUBnTIF) occurs when
data is no longer in transmit FIFO and the transmit shift register (when the FIFO and register are empty).
However, the INTUBnTIT signal or INTUBnTIF signal does not occur if the transmit data register becomes
empty due to RESET input.
Confirm that the UBnSTR.UBnTSF bit is 0 before executing initialization during transmission processing. If
initialization is executed while the UBnTSF bit is 1, the transmit data is not guaranteed.
Confirm that the UBnSTR.UBnTSF bit is 0 before executing initialization during transmission processing (this
can also be done by checking the FIFO transmission end interrupt request signal (INTUBnTIF)).
initialization is executed while the UBnTSF bit is 1, the transmit data is not guaranteed.
To write transmit data to transmit FIFO by DMA control, set the number of transmit data specified as the
trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits to 1 byte; otherwise the operation will not be
guaranteed.
Confirm that the UBnSTR.UBnTSF bit is 0 before executing initialization during transmission processing (this
can also be done by checking the FIFO transmission end interrupt request signal (INTUBnTIF)).
initialization is executed while the UBnTSF bit is 1, the transmit data is not guaranteed.
set the UBnCTL2 register. Then set the UBnCTL0.UBnPWR bit to 1 before setting the other bits.
function to the alternate function. If a low level is input, it is judged that a falling edge is input after the
UBnCTL0.UBnRXE bit has been set to 1, and reception may be started.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
User’s Manual U19601EJ2V0UD
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