UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 272

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
counts each time the valid edge of external event count input is detected. Additionally, the set value of the TAAnCCR0
register is transferred to the CCR0 buffer register.
cleared to 0000H, and a compare match interrupt request signal (INTTAAnCC0) is generated.
(set value of TAAnCCR0 register + 1) times.
270
TAAnCTL1
TAAnCTL0
TAAnIOC0
TAAnIOC2
When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
The INTTAAnCC0 signal is generated each time the valid edge of the external event count input has been detected
(a) TAAn control register 0 (TAAnCTL0)
(b) TAAn control register 1 (TAAnCTL1)
(c) TAAn I/O control register 0 (TAAnIOC0)
(d) TAAn I/O control register 2 (TAAnIOC2)
TAAnCE
0/1
Figure 7-16. Register Setting for Operation in External Event Count Mode (1/2)
0
0
0
TAAnEST
0
0
0
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
TAAnEEE
0
0
0
0
User’s Manual U19601EJ2V0UD
0
0
0
0
TAAnEES1
TAAnOL1
0/1
0
0
0
TAAnEES0 TAAnETS1 TAAnETS0
TAAnCKS2 TAAnCKS1 TAAnCKS0
TAAnOE1 TAAnOL0 TAAnOE0
TAAnMD2 TAAnMD1 TAAnMD0
0/1
0
0
0
0
0
0
0
0
0
0
1
0: Disables TOAAn0 pin output
0: Disables TOAAn1 pin output
Select valid edge of
external event count input
0: Stops counting
1: Enables counting
0, 0, 1:
External event count mode

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