UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 774

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

772
Figure 16-7. Timing of Asynchronous Serial Interface Reception End Interrupt Request Signal (INTUBnTIR)
Receive data register
Cautions 1. Be sure to read all the data (the number of data indicated by the UBnFIS0.UBnRB4 to
Remark
INTUBnTIR
(b) Reception timeout interrupt request signal (INTUBnTITO) (only in FIFO mode)
RXDBn (input)
When the timeout counter function (UBnFIC1.UBnTCE bit = 1) is used in the FIFO mode, the reception
timeout interrupt request signal (INTUBnTITO) occurs if the next data does not come even after the next
data reception wait time specified by the UBnFIC1.UBnTC4 to UBnFIC1.UBnTC0 bits has elapsed and if
data is stored in receive FIFO.
The INTUBnTITO signal does not occur while reception is disabled.
If as many receive data as the number set as the trigger by the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0
bits are not received, the timing of reading less receive data than the specified number can be set by the
INTUBnTITO signal.
Since the timeout counter starts counting at start bit detection, a receive timeout interrupt request signal
does not occur if data of 1 character has not been received.
2. Data is always received with one stop bit (1).
n = 0, 1
(output)
UBnFIS0.UBnRB0 bits) stored in the receive data register (UBnRX register in the single
mode or receive FIFO in the FIFO mode (UBnRXAP register)) even when a reception
error occurs.
Unless the receive data register is read, an overrun error occurs when the next data is
received, causing the reception error status to persist.
If the pending mode is specified in the FIFO mode, however, be sure to clear the FIFO
(UBnFIC0.UBnRFC bit = 1) after reading the data stored in receive FIFO.
In the FIFO mode, the FIFO can be cleared even without reading the data stored in
receive FIFO.
If a parity error or framing error occurs in the FIFO mode, the UBnRXAP register can be
read in 16-bit (halfword) units.
A second stop bit is ignored.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
Start
User’s Manual U19601EJ2V0UD
D0
D1
D2
D6
D7
Parity
Stop