UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1512

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1510
LSTRXDP/LSTTXDP
address of descriptor
Example of location
(5) Last descriptor report
Operation of
Descriptor
descriptor
AHB bus
Current
register
The descriptor base address is
chain
Remark DR: Descriptor read
set to TXDP/TXDP register.
The current descriptor can be reported. Two registers, LSTRXDP and LSTTXDP, hold the address information
of the descriptors processed by the Ethernet controller. The address information of the descriptor that was
processed immediately before can be ascertained by reading these two registers.
The timing of saving the address information of a descriptor to LSTRXDP and LSTTXDP is as follows.
After the data of a descriptor has been transferred and the descriptor has been written back, the address of
the descriptor is copied to LSTRXDP or LSTTXDP.
When the link pointer is read, the address information of the next descriptor can be read from the BAP bit.
Therefore, the address of the link pointer is copied to LSTRXDP or LSTTXDP.
Buffer address pointer
Descriptor base address
Descriptor base address
DW: Descriptor write-back
DR
Descriptor 1
Reset value
DMA transfer
DW
Figure 23-22. Timing of Copying the Last Descriptor
Base address + 8
Buffer address pointer
Base address
CHAPTER 23 ETHERNET CONTROLLER
DR
Base address + 8
Descriptor 2
DMA transfer
User’s Manual U19601EJ2V0UD
DW
Base address + 16
Base address + 8
Link address pointer
Base address + 16
DR
(New address)
T = 1, E = 0
Base address + 16
New address
Buffer address pointer
DR
Descriptor 2
New address
DMA transfer
DW
New address + 8
New address New address + 8
New address + 8
DR
End of chain
T = 1, E = 1
0000 0000H