UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 789

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UPD70F3786GJ-GAE-AX

Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet

Specifications of UPD70F3786GJ-GAE-AX

Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
(6) Example of continuous reception processing in FIFO mode (CPU control)
Notes 1.
Remark
Set UARTBn-related registers
INTUBnTIRE interrupt = 1?
INTUBnTITO interrupt = 1?
UBnRXE = 1 (UBnCTL0)
UBnRXE = 0 (UBnCTL0)
Check UBnFIS0 register
Read receive FIFO
Reception ended?
Clear receive FIFO
Figure 16-18. Example of Continuous Reception Processing in FIFO Mode (CPU Control)
2.
n = 0, 1
START
Read as many receive data as the number set as the trigger by the UBnFIC2.UBnRT3 to
UBnFIC2.UBnRT0 bits from receive FIFO in the pending mode (UBnFIC0.UBnIRM bit = 0). In the
pointer mode (UBnIRM bit = 1), reference the UBnFIS0.UBnRB4 to UBnFIS0.UBnRB0 bits and
read as many data as the number of bytes stored in receive FIFO from receive FIFO.
Read as many data (remaining receive data less than the number set as the trigger) as the
number of bytes stored in receive FIFO from receive FIFO by referencing the UBnFIS0.UBnRB4 to
UBnFIS0.UBnRB0 bits.
END
Yes
Yes
No
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
Note 2
: Enable reception
: Disable reception
: Read receive data remaining in receive FIFO
Yes
No
No
INTUBnTIR interrupt = 1?
Read receive FIFO
Error processing in
FIFO mode
User’s Manual U19601EJ2V0UD
Yes
Note 1
No
: Reading from receive FIFO enabled?
: Read receive data
: Reception error occurred?
: Reception timeout occurred?
: Reading all receive data ended?
787

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