UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1481

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark TPID:
Remark DA:
(2) VLAN frames
(3) Pause control frames
Preamble
7 bytes
(f) Frame check sequence (FCS)
The structure of a VLAN frame (Qtag frame) is slightly different from that of a basic frame.
A 4-byte VLAN header is inserted immediately after the source address field. As a result, the minimum packet
length of a VLAN frame is 64 bytes and the maximum packet length is 1,522 bytes.
The Ethernet controller has a VLAN frame detection function. If a transmit packet or a receive packet is
identified as a VLAN frame, packet processing is performed based on the receive packet length.
Caution The Ethernet controller recognizes the value set to the VLTP.VLTP[15:0] bits as a VLAN frame
A pause control frame is a 64-byte packet with a dedicated format.
The destination address field has a fixed value of 01-80-C2-00-00-01H.
The type/length field has a value of 8808H, which indicates a control frame, and the opcode has a value of
0001H, which indicates pause control. The parameter field has the value specified by the PAUSETM register.
The unused area following the parameter field is filled with PAD data consisting of zeros.
Preamble
7 bytes
The frame check sequence field is used to write 32-bit CRC code to check the transfer data.
The Ethernet controller can automatically append a CRC to a transmit frame.
TCI:
TPID+TCI: VLAN header
TYPE/LEN:
OPCODE:
PARAMETER: Pause command parameter (specified by PAUSETM register)
PAD:
1 byte
(TPID). The default value is 0000H. For details, refer to 23.4.1 (10) VLTP: VLAN type register.
SFD
1 byte
SFD
Tag Protocol ID
Tag Control Information
Fixed address (01-80-C2-00-00-01H)
Type of MAC control frame (88-08H)
Pause Op-code (00-01H)
All bits are filled with zero (00H)
6 bytes
6 bytes
DA
DA
Figure 23-5. Pause Control Frame Structure
CHAPTER 23 ETHERNET CONTROLLER
Figure 23-4. VLAN Frame Structure
6 bytes
6 bytes
SA
SA
User’s Manual U19601EJ2V0UD
2 bytes
TYPE
2 bytes
TPID
2 bytes
CODE
OP
2 bytes
TCI
METER
2 bytes
PARA
2 bytes
TYPE/
LEN
PAD (00H)
46 to 1,500 bytes
DATA+PAD
42 bytes
4 bytes
4 bytes
FCS
FCS
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