UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1189

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 3. The SET_FEATURE request sets the UF0 device status register L (UF0DSTL) and UF0 EPn status
Cautions 1. The sequence of control transfer defined by the Universal Serial Bus Specification is not
Remarks 1. Df: Default state, Ad: Addressed state, Cf: Configured state
4. If the wValue is not the default value, an automatic STALL response is made.
2. An ACK response is made even when the host transmits data other than a Null packet in the
3. If the wLength value is 00H during control transfer (read) of FW processing, a Null packet is
2. n = 0 to 4
3. $$: Valid endpoint number including transfer direction
4. ? and #: Value transmitted from host (information on Interface numbers 0 to 4)
register L (UF0EnSL) (n = 0 to 4, 7) when ACK is received in the status stage. If the E0HALT bit of the
UF0E0SL register is set, a STALL response is made in the status stage or data stage of control transfer
for a request other than the GET_STATUS Endpoint0 request, SET_FEATURE Endpoint0 request, and a
request generated by the CPUDEC interrupt request, until the CLEAR_FEATURE Endpoint0 request is
received. A STALL response to an unsupported request does not set the E0HALT bit of the UF0E0SL
register to 1, and the STALL response is cleared as soon as the next SETUP token has been received.
satisfied under the following conditions.
conditions.
• If an IN/OUT token is suddenly received without a SETUP stage
• If DATA PID1 is sent in the data phase of the SETUP stage
• If a token of 128 addresses or more is received
• If the request data transmitted in the SETUP stage is of less than 8 bytes
status stage.
automatically transmitted for control transfer (without data).
automatically transmit a Null packet.
It is determined by the setting of the UF0 active interface number register (UF0AIFN) whether a
request with Interface number 1 to 4 is correctly responded to, depending on whether the Interface
number of the target is valid or not.
The valid endpoint is determined by the currently set Alternate Setting number (see 22.6.3 (36) UF0
active alternative setting register (UF0AAS), (38) UF0 endpoint 1 interface mapping register
(UF0E1IM) to (42) UF0 endpoint 7 interface mapping register (UF0E7IM)).
It is determined by the UF0 active interface number register (UF0AIFN) and UF0 active alternative
setting register (UF0AAS) whether an Alternate Setting request corresponding to each Interface
number is correctly responded to or not, depending on whether the Interface number and Alternate
Setting of the target are valid or not.
CHAPTER 22 USB FUNCTION CONTROLLER (USBF)
User’s Manual U19601EJ2V0UD
The operation is not guaranteed under these
The FW request does not
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