UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1399

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15
14
13
12
11
10
(22) CAM1: Carry mask register 1
Bit
This register is used to mask the INTFTMOV signal that is generated when a statistics counter has overflowed
and the corresponding bit of the CAR1 register has been set to 1.
Each bit of this register can be masked.
Access
Address
Default value 0000 0000H. This register is cleared to its default value by all types of resets.
Caution Be sure to set bits 31 to 16 to “0”.
M1VT
M1UT
M1BT
M1MT
M1PT
M1TB
M1VT
M1FE
R/W
R/W
31
23
15
Name
R
R
0
0
7
This register can be read and written in 32-bit units.
002E 0130H
M1UT
M1TF
RVBT counter overflow interrupt mask bit
TUCA counter overflow interrupt mask bit
TBCA counter overflow interrupt mask bit
TMCA counter overflow interrupt mask bit
TPKT counter overflow interrupt mask bit
TBYT counter overflow interrupt mask bit
R/W
R/W
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
0: Interrupt generation is enabled (not masked).
1: Interrupt generation is disabled (masked).
30
22
14
R
R
0
0
6
CHAPTER 23 ETHERNET CONTROLLER
M1BT
M1OT
R/W
R/W
29
21
13
R
R
0
0
5
User’s Manual U19601EJ2V0UD
M1MT
M1SF
R/W
R/W
28
20
12
R
R
0
0
4
M1PT
M1BR
R/W
R/W
27
19
11
R
R
0
0
3
Description
M1MR
M1TB
R/W
R/W
26
18
10
R
R
0
0
2
M1MX
M1PR
R/W
R/W
25
17
R
R
0
0
9
1
M1RB
M11K
R/W
R/W
24
16
R
R
0
0
8
0
(1/2)
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